Integrated circuit and method of manufacturing same

ABSTRACT

A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.

PRIORITY CLAIM

This application is a continuation of U.S. application Ser. No. 15/966,693, filed Apr. 30, 2018, now U.S. Pat. No. 10,503,863, issued Dec. 10, 2019, which claims the benefit of U.S. Provisional Application No. 62/552,220, filed Aug. 30, 2017, which is herein incorporated by reference in its entirety.

BACKGROUND

The recent trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices which consume less power yet provide more functionality at higher speeds. The miniaturization process has also resulted in stricter design and manufacturing specifications as well as reliability challenges. Various electronic design automation (EDA) tools generate, optimize and verify standard cell layout designs for integrated circuits while ensuring that the standard cell layout design and manufacturing specifications are met.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flowchart of a method of manufacturing an integrated circuit, in accordance with some embodiments.

FIG. 2 is a flowchart of a method of generating a layout design of an integrated circuit based on a set of design rules, in accordance with some embodiments.

FIG. 3A is a diagram of a layout design of an integrated circuit, in accordance with some embodiments.

FIG. 3B is a diagram of a layout design of an integrated circuit, in accordance with some embodiments.

FIG. 4A is a perspective diagram of an integrated circuit, in accordance with some embodiments.

FIG. 4B is a perspective diagram of an integrated circuit, in accordance with some embodiments.

FIG. 5A is a diagram of a layout design of an integrated circuit, in accordance with some embodiments.

FIG. 5B is a diagram of a layout design of an integrated circuit, in accordance with some embodiments.

FIG. 5C is a diagram of a layout design of an integrated circuit, in accordance with some embodiments.

FIG. 6 is a diagram of a layout design of an integrated circuit, in accordance with some embodiments.

FIG. 7 is a diagram of a layout design of an integrated circuit, in accordance with some embodiments.

FIG. 8 is a diagram of a layout design of an integrated circuit, in accordance with some embodiments.

FIG. 9 is a diagram of a layout design of an integrated circuit, in accordance with some embodiments.

FIGS. 10A-10B is a flowchart of a method of generating a layout design of an integrated circuit, in accordance with some embodiments.

FIG. 11 is a block diagram of a system for designing an IC layout design, in accordance with some embodiments.

FIG. 12 is a block diagram of an integrated circuit (IC) manufacturing system, and an IC manufacturing flow associated therewith, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In accordance with some embodiments, a method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The integrated circuit has a first gate. Generating the layout design includes generating a set of gate layout patterns, generating a cut feature layout pattern and generating a first via layout pattern. The cut feature layout pattern extends in a first direction, is located on a first layout level and overlaps at least a first gate layout pattern. The set of gate layout patterns extends in a second direction and is located on the first layout level. The first via layout pattern is over the first gate layout pattern, and is separated in the second direction from the cut feature layout pattern by a first distance. The first distance satisfies a first design rule.

In some embodiments, by satisfying one or more design rules, layout design and corresponding integrated circuits manufactured by the layout designs account for process limitations resulting in integrated circuits capable of being manufactured with a higher yield compared to other approaches. In some embodiments, by satisfying one or more design rules, layout design and corresponding integrated circuits manufactured by the layout designs are smaller compared to other approaches. In some embodiments, by satisfying one or more design rules, layout design and corresponding integrated circuits manufactured by the layout designs have higher gate density compared to other approaches. In some embodiments, by using one or more layout designs of the present application, the integrated circuit manufactured by the corresponding one or more layout designs has a gate density that is at least 10% greater compared to other approaches.

In some embodiments, the set of design rules includes spacing requirements between each of the vias in the layout design. In some embodiments, the set of design rules includes pitch spacing requirements between via layout patterns.

In some embodiments, the set of design rules includes pitch spacing requirements between fin layout patterns of layout designs. In some embodiments, the set of design rules includes spacing requirements between via layout patterns and cut feature layout patterns. In some embodiments, the set of design rules includes spacing requirements between active region layout patterns and cut feature layout patterns.

In some embodiments, the set of design rules includes spacing requirements between active region layout patterns. In some embodiments, the set of design rules includes one or more metal over diffusion (MD) design rules. In some embodiments, the set of design rules includes one or more via over gate (VG) landing design rules. In some embodiments, the set of design rules includes one or more metal zero (M0) metal track design rules.

FIG. 1 is a flowchart of a method 100 of manufacturing an integrated circuit in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method 100 depicted in FIG. 1, and that some other processes may only be briefly described herein. In some embodiments, the method 100 is usable to form integrated circuits, such as integrated circuit 400A (FIG. 4A) or integrated circuit 400B (FIG. 4B). In some embodiments, the method 100 is usable to form integrated circuits having similar structural relationships as one or more of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9).

In operation 102 of method 100, a layout design of an integrated circuit is generated based on a set of design rules. In some embodiments, the layout design of method 100 includes one or more layout designs, such as one or more of layout design 300A (FIG. 3A), layout design 300B (FIG. 3B), layout design 500A (FIG. 5A), layout design 500B (FIG. 5B), layout design 600 (FIG. 6), layout design 700 (FIG. 7), layout design 800 (FIG. 8) or layout design 900 (FIG. 9) of an integrated circuit, such as integrated circuit 400A (FIG. 4A) or integrated circuit 400B (FIG. 4B).

In some embodiments, operation 102 of method 100 is performed by a processing device (e.g., processor 1102 (FIG. 11)) configured to execute instructions for generating a layout design, such as layout design 300A (FIG. 3A), layout design 300B (FIG. 3B), layout design 500A (FIG. 5A), layout design 500B (FIG. 5B), layout design 600 (FIG. 6), layout design 700 (FIG. 7), layout design 800 (FIG. 8) or layout design 900 (FIG. 9). In some embodiments, one or more of layout design 300A (FIG. 3A), layout design 300B (FIG. 3B), layout design 500A (FIG. 5A), layout design 500B (FIG. 5B), layout design 600 (FIG. 6), layout design 700 (FIG. 7), layout design 800 (FIG. 8) or layout design 900 (FIG. 9) is a graphic database system (GDSII) file format. In some embodiments, operation 102 of method 100 is utilized to generate one or more of layout design 300A (FIG. 3A), layout design 300B (FIG. 3B), layout design 500A (FIG. 5A), layout design 500B (FIG. 5B), layout design 600 (FIG. 6), layout design 700 (FIG. 7), layout design 800 (FIG. 8) or layout design 900 (FIG. 9).

In some embodiments, the set of design rules of method 100 or method 200 (FIG. 2) includes one or more design rules of layout design 300A-300B (FIGS. 3A-3B), layout design 500A-500B (FIGS. 5A-5B) or layout design 600-900 (FIGS. 6-9). In some embodiments, the set of design rules of method 100 or method 200 (FIG. 2) includes one or more design rules of formulas 1-21 (described in FIGS. 6-9), VG landing design rules of layout design 500A-500B (FIGS. 5A-5B), M0 metal track design rules of layout design 500A-500B (FIGS. 5A-5B) or MD design rules of layout design 300A-300B (FIGS. 3A-3B).

Method 100 continues with operation 104, where the integrated circuit (e.g., integrated circuit 400A-400B (FIGS. 4A-4B) is manufactured based on one or more of layout design 300A (FIG. 3A), layout design 300B (FIG. 3B), layout design 500A (FIG. 5A), layout design 500B (FIG. 5B), layout design 600 (FIG. 6), layout design 700 (FIG. 7), layout design 800 (FIG. 8) or layout design 900 (FIG. 9).

In some embodiments, operation 104 comprises manufacturing at least one mask based on one or more of layout design 300A (FIG. 3A), layout design 300B (FIG. 3B), layout design 500A (FIG. 5A), layout design 500B (FIG. 5B), layout design 600 (FIG. 6), layout design 700 (FIG. 7), layout design 800 (FIG. 8) or layout design 900 (FIG. 9), and manufacturing the integrated circuit (e.g., integrated circuit 400A-400B (FIGS. 4A-4B) based on the at least one mask. In some embodiments, operation 104 of method 100 is utilized to manufacture integrated circuit (e.g., integrated circuit 400A-400B (FIGS. 4A-4B) based on one or more of layout design 300A (FIG. 3A), layout design 300B (FIG. 3B), layout design 500A (FIG. 5A), layout design 500B (FIG. 5B), layout design 600 (FIG. 6), layout design 700 (FIG. 7), layout design 800 (FIG. 8) or layout design 900 (FIG. 9).

Method 100 continues with operation 106, where a portion of a gate (e.g., gate 404 a, 404 b) is removed thereby forming a first gate structure (e.g., gate 404 a or 404 b) and a second gate structure (e.g., the other of gate 404 a or 404 b) of integrated circuit 400A-400B.

In some embodiments, the portion of the gate (e.g., gate 404 a, 404 b) that is removed in operation 106 is identified in one or more of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9) by one or more cut feature layout patterns 308 a, 308 b, 608 a, 608 b, 608 c, 608 d, 708 a, 708 b, 808 a, 808 b, 808 e, 808 f, 908 a or 908 b of the set of cut feature layout patterns 308, 608, 708, 808 or 908. In some embodiments, operation 106 of method 100 is referred to as a cut-poly (CPO) process. In some embodiments, operation 106 results in the formation of integrated circuit 400A-400B (FIGS. 4A-4B). In some embodiments, the removed gate portion of gate 404 a and gate 404 b is referred to as a cut region.

In some embodiments, operation 106 is performed by a removal process. In some embodiments, the removal process includes one or more etching processes suitable to remove a portion of the gate (e.g., gate 404 a, 404 b). In some embodiments, the etching process of operation 106 includes identifying a portion of the gate (e.g., gate 404 a, 404 b) that is to be removed, and etching the portion of the gate (e.g., gate 404 a, 404 b) that is to be removed. In some embodiments, a mask is used to specify portions of the gate (e.g., gate 404 a, 404 b) that are to be cut or removed. In some embodiments, the mask is a hard mask. In some embodiments, the mask is a soft mask. In some embodiments, etching corresponds to plasma etching, reactive ion etching, chemical etching, dry etching, wet etching, other suitable processes, any combination thereof, or the like.

In some embodiments, one or more of operations 102, 104 or 106 is not performed.

FIG. 2 is a flowchart of a method 200 of generating a layout design of an integrated circuit based on a set of design rules in accordance with some embodiments.

It is understood that additional operations may be performed before, during, and/or after the method 200 depicted in FIG. 2, and that some other processes may only be briefly described herein. In some embodiments, the method 200 is usable to generate one or more layout designs, such as layout design 300A, 300B, 500A, 500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9) of an integrated circuit, such as integrated circuit 400A (FIG. 4A) or integrated circuit 400B (FIG. 4B) based on a set of design rules (FIGS. 3A-3B, 5A-5B & 6-9). Method 200 is an embodiment of operation 102 of method 100 (FIG. 1).

In operation 202 of method 200, a first layout design (e.g., layout design 300A of FIG. 3A or layout design 500A of FIG. 5A) of an integrated circuit, such as integrated circuit 400A or 400B (FIGS. 4A-4B), is generated. In some embodiments, the first layout design of method 200 includes one or more layout designs, such as layout design 300B, 500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9).

In operation 204 of method 200, a determination is made whether the first layout design (e.g., layout design 300A of FIG. 3A or layout design 500A of FIG. 5A) or a revised first layout design (e.g., layout design 300B of FIG. 3B or layout design 500B of FIG. 5B) complies with a set of design rules (FIGS. 3A-3B, 5A-5B and 6-9). In some embodiments, the revised first layout design (e.g., layout design 300B of FIG. 3B or layout design 500B of FIG. 5B) is generated in operation 206.

In some embodiments, the set of design rules includes spacing requirements between each of the vias in the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9)). For example, if the vias in the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9)) are not sufficiently separated from each other, the vias cannot be consistently manufactured due to shorted out vias.

In some embodiments, the set of design rules includes pitch spacing requirements (e.g., one or more of poly pitch P1A, P1B, P1C or P1D or distance DVG_HA, DVG_VA, DVG_HB, DVG_VB, DVG_VC, DVG_VC1, DVG_VC2, DVG_VD1, DVG_VD2 in FIGS. 6-9) between via layout patterns of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9).

In some embodiments, the set of design rules includes pitch spacing requirements (e.g., pitch P2A, P2B, P2C or P2D in FIGS. 6-9) between fin layout patterns of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9).

In some embodiments, the set of design rules includes spacing requirements (e.g., distance S1A, S1B, S1C or S1D in FIGS. 6-9) between via layout patterns and cut feature layout patterns of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9).

In some embodiments, the set of design rules includes spacing requirements (e.g., distance S2A, S2B, S2C or S2D in FIGS. 6-9) between active region layout patterns and cut feature layout patterns of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9).

In some embodiments, the set of design rules includes spacing requirements (e.g., distance S3A, S3B, S3C or S3D in FIGS. 6-9) between active region layout patterns of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9). In some embodiments, one or more active region layout patterns of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9) define corresponding active regions in an integrated circuit manufactured by layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9). In some embodiments, one or more active regions correspond to source and/or drain diffusion portions of at least one transistor having a first dopant type. In some embodiments, the first dopant type is a p-dopant type. In some embodiments, the first dopant type is an n-dopant type.

In some embodiments, the set of design rules includes one or more design rules of formulas 1-21 of layout design 600-900 (FIGS. 6-9). In some embodiments, the set of design rules includes one or more MD design rules of layout design 300A-300B (FIGS. 3A-3B). In some embodiments, the set of design rules includes one or more VG landing design rules of layout design 500A-500B (FIGS. 5A-5B). In some embodiments, the set of design rules includes one or more M0 metal track design rules of layout design 500A-500B (FIGS. 5A-5B).

In some embodiments, the set of design rules depends upon the number of masks or colors used in the layout design (e.g., layout design 300A-300B, 500A-500B, 600-900 of FIG. 3A-3B, 5A-5B or 6-9).

In some embodiments, one or more of the set of design rules of layout design (e.g., layout design 300A-300B, 500A-500B, 600-900 of FIG. 3A-3B, 5A-5B or 6-9) are implemented in method 100 or 200 in conjunction with other design rules of layout design (e.g., layout design 300A-300B, 500A-500B, 600-900 of FIG. 3A-3B, 5A-5B or 6-9). In some embodiments, one or more of the set of design rules of layout design (e.g., layout design 300A-300B, 500A-500B, 600-900 of FIG. 3A-3B, 5A-5B or 6-9) are implemented in method 100 or 200 separately from other design rules of layout design (e.g., layout design 300A-300B, 500A-500B, 600-900 of FIG. 3A-3B, 5A-5B or 6-9). In some embodiments, the set of design rules of method 100 or 200 are specified by a user interface (e.g., user interface 1118 (FIG. 11)).

In some embodiments, determining if the first layout design (e.g., layout design 300A of FIG. 3A or layout design 500A of FIG. 5A) or the revised first layout design (e.g., layout design 300B of FIG. 3B or layout design 500B of FIG. 5B) complies with the set of design rules of operation 204 comprises performing a design rule check of the first layout design (e.g., layout design 300A of FIG. 3A or layout design 500A of FIG. 5A) or the revised first layout design (e.g., layout design 300B of FIG. 3B or layout design 500B of FIG. 5B) based on the set of design rules.

If the first layout design (e.g., layout design 300A of FIG. 3A or layout design 500A of FIG. 5A) or the revised first layout design (e.g., layout design 300B of FIG. 3B or layout design 500B of FIG. 5B) is determined to have complied with the set of design rules, then method 200 proceeds to operation 208. If the first layout design (e.g., layout design 300A of FIG. 3A or layout design 500A of FIG. 5A) or the revised first layout design (e.g., layout design 300B of FIG. 3B or layout design 500B of FIG. 5B) is determined to not have complied with the set of design rules, then method 200 proceeds to operation 206.

In operation 206 of method 200, the first layout design (e.g., layout design 300A of FIG. 3A or layout design 500A of FIG. 5A) is revised based on the set of design rules. In some embodiments, the revised first layout design includes one or more of layout design 300B of FIG. 3A or layout design 500B of FIG. 5B.

In some embodiments, operation 206 comprises generating a revised first layout design (e.g., layout design 300B of FIG. 3B or layout design 500B of FIG. 5B) based on the first layout design (e.g., layout design 300A of FIG. 3A or layout design 500A of FIG. 5A) and the set of design rules. In some embodiments, revising the first layout design during operation 206 comprises generating a second layout design based on the set of design rules, the second layout design corresponding to the revised first layout design (e.g., layout design 300B of FIG. 3B or layout design 500B of FIG. 5B).

In operation 208 of method 200, the first layout design or the revised layout design (e.g., layout design 300B of FIG. 3B or layout design 500B of FIG. 5B) is output by system 1100 (FIG. 11). In some embodiments, the first layout design or the revised layout design (e.g., layout design 300B, 500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9) of operation 208 complies with the set of design rules. In some embodiments, one or more of operations 206 or 208 is not performed. In in some embodiments, operation 208 generates a second layout design. In some embodiments, the second layout design of operation 208 corresponds to the first layout design or the revised first layout design.

For example, in some embodiments, if layout design 300 a of FIG. 3A or layout design 500A of FIG. 5A corresponds to the first layout design of method 200, and operation 204 determines that layout design 300A of FIG. 3A or layout design 500A of FIG. 5A does not comply with the set of design rules, then layout design 300A of FIG. 3A or layout design 500A of FIG. 5A, is not output as the first layout design after execution of operation 208.

In some embodiments, the first layout design of method 200 includes one or more of layout designs 600-900 (FIGS. 6-9), each of which comply with the set of design rules. In these embodiments, in operation 208, one or more of layout designs 600-900 (FIGS. 6-9) is output as the first layout design that complies with the set of design rules. In some embodiments, operation 208 comprises outputting the second layout design, the second layout design complying with the set of design rules.

In some embodiments, the first layout design or the revised first layout design of method 200 includes one or more of layout designs 600-900 (FIG. 3A-3B, 5A-5B or 6-9). In some embodiments, one or more operations of 202-208 of method 200 is performed by a processing device (e.g., processor 1102 (FIG. 11)) configured to execute instructions for generating one or more of layout design 300A, 300B, 500A, 500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9).

FIG. 3A is a diagram of a layout design 300A of an integrated circuit, in accordance with some embodiments.

Layout design 300A is usable to manufacture an integrated circuit similar to integrated circuit 400A of FIG. 4A. Components that are the same or similar to those in each of FIG. 3A-3B, 5A-5B or 6-9 are given the same reference numbers, and similar detailed description thereof is thus omitted. In some embodiments, layout design 300A corresponds to the first layout design of an integrated circuit after operation 202 in method 200 (FIG. 2).

Layout design 300A includes one or more gate layout patterns 304 a, 304 b (collectively referred to as a “set of gate layout patterns 304”) being located on a first layout level of layout design 300A. In some embodiments, the first layout level of one or more of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9) corresponds to the poly layout level. Each of the layout patterns 304 a, 304 b of the set of gate layout patterns 304 is separated from an adjacent layout pattern of the set of gate layout patterns 304 in a first direction X by a poly pitch (not labeled). The set of gate layout patterns extends in a second direction Y different from the first direction X. In some embodiments, the first direction X is perpendicular to the second direction Y. The set of gate layout patterns 304 is usable to manufacture a corresponding set of gates 404 of an integrated circuit 400A-400B (FIGS. 4A-4B). Other configurations or quantities of layout patterns in the set of gate layout patterns 304 are within the scope of the present disclosure.

Layout design 300A further includes one or more power rail layout patterns 306 a, 306 b (collectively referred to as a “set of power rail layout patterns 306”) extending in the first direction X, and being located on a second layout level different from the first layout level. In some embodiments, the second layout level corresponds to the metal zero (M0) layer of one or more of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9). In some embodiments, the second layout level is above the first layout level. In some embodiments, the second layout level is below the first layout level. The set of power rail layout patterns 306 is usable to manufacture a corresponding set of power rails (not shown) of an integrated circuit, such as integrated circuit 400A-400B (FIGS. 4A-4B). In some embodiments, the set of power rails (not shown) are configured to provide a first supply voltage VDD or second supply voltage VSS to the integrated circuit, such as integrated circuit 400A-400B. In some embodiments, each power rail layout pattern of the set of power rail layout patterns 306 is located along a corresponding edge of a standard cell of layout design 300A. Other configurations or quantities of layout patterns in the set of power rail layout patterns 306 are within the scope of the present disclosure.

Layout design 300A further includes a set of cut feature layout patterns 308 extending in the first direction X. The set of cut feature layout patterns 308 includes one or more cut feature layout patterns. The set of cut feature layout patterns 308 overlaps at least gate layout pattern 304 a or gate layout pattern 304 b of the set of gate layout patterns 304. In some embodiments, each cut feature layout pattern of the set of cut feature layout patterns 308 overlaps corresponding gate layout patterns 304 a, 304 b of the set of gate layout patterns 304. Each layout pattern of the set of cut feature layout patterns 308 has a pattern width in the second direction Y, and a pattern length in the first direction X. In some embodiments, cut feature layout pattern 308 is usable to identify a location of gates 404 a and 404 b (FIG. 4A) of integrated circuit 400 that are removed during operation 106 of method 100 (FIG. 1). The removed gate portion of gates 404 a and 404 b is also referred to as a cut region. In some embodiments, the set of gate layout patterns 304 and the set of cut feature layout patterns 308 are located on the first layout level. Other configurations or quantities of patterns in the set of cut feature layout patterns 308 are within the scope of the present disclosure.

Layout design 300A further includes metal over diffusion layout patterns 310 a, 310 b (collectively referred to as a “set of metal over diffusion layout patterns 310”) extending in the second direction Y. Each of the layout patterns of the set of metal over diffusion layout patterns 310 is separated from an adjacent layout pattern of the set of metal over diffusion layout patterns 310 in at least the first direction X or the second direction Y. The set of metal over diffusion layout patterns 310 is located on the first layout level. In some embodiments, the set of metal over diffusion layout patterns 310 is located on the metal over diffusion (MD) portion of the first layout level. The set of metal over diffusion layout patterns 310 is usable to manufacture a corresponding set of contacts 410 a, 410 b (FIG. 4A) of integrated circuit 400. The set of metal over diffusion layout patterns 310 are over one or more active region layout patterns (shown in FIGS. 6-9). In some embodiments, the one or more active region layout patterns (shown in FIGS. 6-9) are referred to as oxide diffusion (OD) region layout patterns. In some embodiments, OD region layout patterns are usable to manufacture source or drain regions of one or more transistors. In some embodiments, the set of metal over diffusion layout patterns 310 are over one or more OD region layout patterns. Other configurations or quantities of layout patterns in the set of metal over diffusion layout patterns 310 are within the scope of the present disclosure.

Layout design 300A further includes one or more conductive feature layout patterns 314 a, 314 b, 314 c, 314 d, 314 e, 314 f (collectively referred to as a “set of conductive feature layout patterns 314”) extending in the first direction X and being located on the second layout level. Set of conductive feature layout patterns 314 overlaps at least the set of gate layout patterns 304 or the set of metal over diffusion layout patterns 310. In some embodiments, one or more conductive feature layout pattern of the set of conductive feature layout patterns 314 is separated from an adjacent conductive feature layout pattern of the set of conductive feature layout patterns 314 in at least first direction X or the second direction Y. For example, conductive feature layout pattern 314 a is separated in the first direction X from conductive feature layout pattern 314 e. Similarly, conductive feature layout pattern 314 c is separated in the first direction X from conductive feature layout pattern 314 f.

The set of conductive feature layout patterns 314 is usable to manufacture a corresponding set of conductive structures 414 of the integrated circuit, such as integrated circuit 400A-400B (FIGS. 4A-4B). For example, conductive feature layout patterns 314 b, 314 d are usable to manufacture corresponding conductive structures 414 b, 414 d of integrated circuit 400A.

Conductive feature layout patterns 314 a, 314 b, 314 c, 314 d of the set of conductive feature layout patterns 314 overlap a corresponding gridline 302 a, 302 b, 302 c, 302 d (collectively referred to as “gridlines 302”). Conductive feature layout pattern 314 e, 314 f of the set of conductive feature layout patterns 314 overlaps corresponding gridline 302 a, 302 c.

Gridlines 302 are arranged in the first direction X. Each gridline of gridlines 302 is separated from an adjacent gridline of gridlines 302 by a pitch P1 (not labelled) in the second direction Y. In some embodiments, gridlines 302 define regions where conductive feature layout patterns in the set of conductive feature layout patterns 314 are positioned. In some embodiments, each of the gridlines 302 defines a corresponding M0 metal track position. In some embodiments, layout design 300A includes four M0 metal track positions (e.g., conductive feature layout patterns 314 a, 314 b, 314 c, 314 d) between the set of power rail layout patterns 306. As shown in FIG. 3A, a signal V1 is applied to each of conductive feature layout patterns 314 b and 314 d. Other configurations or quantities of conductive feature layout patterns in the set of conductive feature layout patterns 314 or gridlines 302 are within the contemplated scope of the present disclosure.

Layout design 300A further includes one or more via layout patterns 320 a, 322 a (collectively referred to as a “set of via layout patterns 320”) over the set of metal over diffusion layout patterns 310. Set of via layout patterns 320 is usable to manufacture a corresponding set of vias 420 of integrated circuit 400A-400B (FIGS. 4A-4B). Set of via layout patterns 320 are positioned at a via over diffusion (VD) level of layout design 300. In some embodiments, the VD level is between the first layout level and the second layout level of one or more of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9).

Via layout pattern 320 a is located where conductive feature layout pattern 314 d overlaps metal over diffusion layout pattern 310 b of set of metal over diffusion layout patterns 310. Via layout pattern 320 a is between conductive feature layout pattern 314 d and metal over diffusion layout pattern 310 b of the set of metal over diffusion layout patterns 310.

Via layout pattern 322 a is located where conductive feature layout pattern 314 b overlaps metal over diffusion layout pattern 310 a of the set of metal over diffusion layout patterns 310. Via layout pattern 322 a is between conductive feature layout pattern 314 b and metal over diffusion layout pattern 310 a of the set of metal over diffusion layout patterns 310. Other configurations or quantities of layout patterns in the set of via layout patterns 320 are within the scope of the present disclosure.

Layout design 300A further includes one or more via layout patterns 330, 332 (collectively referred to as a “set of via layout patterns 340”) over the set of gate layout patterns 304. Set of via layout patterns 340 is usable to manufacture a corresponding set of vias 430 of integrated circuit 400A-400B. Via layout patterns 330, 332 is usable to manufacture corresponding via 430, 432 of integrated circuit 400A-400B (FIGS. 4A-4B). Set of via layout patterns 340 are positioned at a via over gate (VG) level of layout design 300. In some embodiments, the VG level is between the first layout level and the second layout level of one or more of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9).

Via layout pattern 330 is located where power rail layout pattern 306 a overlaps the gate layout pattern 304 a of the set of gate layout patterns 304. Via layout pattern 330 is between power rail layout pattern 306 a and gate layout pattern 304 a of the set of gate layout patterns 304.

Via layout pattern 332 is located where power rail layout pattern 306 b overlaps gate layout pattern 304 a of the set of gate layout patterns 304. Via layout pattern 332 is between power rail layout pattern 306 b and gate layout pattern 304 a of the set of gate layout patterns 304. Other configurations or quantities of layout patterns in the set of via layout patterns 340 are within the scope of the present disclosure.

One or more of layout designs 300A-300B, 500A-500B or 600-900 (FIG. 3A-3B, 5A-5B or 6-9) corresponds to a layout design of at least a portion of one or more cells. In some embodiments, a cell is a standard cell. In some embodiments, the cell includes one or more cross-coupled structures. In some embodiments, cross-coupled structures include at least two structures coupled to each other and share a same signal (e.g., control signal, supply voltage VDD or VSS). In some embodiments, a standard cell is a logic gate cell. In some embodiments, a logic gate cell includes an AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, or clock cells. In some embodiments, a standard cell is a memory cell. In some embodiments, a memory cell includes a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), a magnetoresistive RAM (MRAM) or read only memory (ROM). In some embodiments, a standard cell includes one or more active or passive elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), FinFETs, and planar MOS transistors with raised source/drain. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors.

FIG. 3B is a diagram of a layout design 300B of an integrated circuit, in accordance with some embodiments.

Layout design 300B is usable to manufacture an integrated circuit similar to integrated circuit 400B of FIG. 4B. In some embodiments, layout design 300B corresponds to the revised first layout design of an integrated circuit after operation 206 in method 200 (FIG. 2).

Layout design 300B is a variation of layout design 300A (FIG. 3A).

In comparison with layout design 300A of FIG. 3A, set of conductive feature layout patterns 316 of FIG. 3B replaces set of conductive feature layout patterns 314, and similar detailed description is therefore omitted.

The set of conductive feature layout patterns 316 includes one or more conductive feature layout patterns 316 a, 316 b, 316 c, 316 d, 316 e, 316 f and 316 g. Conductive feature layout pattern 316 c is usable to manufacture conductive structure 416 c of integrated circuit 400B (FIG. 4B).

Conductive feature layout patterns 316 a and 316 e replace corresponding conductive feature layout patterns 314 a and 314 e, and similar detailed description is therefore omitted. Conductive feature layout patterns 316 b and 316 f replace conductive feature layout pattern 314 b, and similar detailed description is therefore omitted. Conductive feature layout pattern 316 c replaces conductive feature layout patterns 314 c, 314 f, and similar detailed description is therefore omitted. Conductive feature layout patterns 316 d and 316 g replace conductive feature layout pattern 314 d, and similar detailed description is therefore omitted.

In comparison with layout design 300A of FIG. 3A, via layout pattern 322 b of FIG. 3B replaces via layout pattern 322 a, and similar detailed description is therefore omitted. Via layout pattern 322 b is usable to manufacture via 422 b of integrated circuit 400B (FIG. 4B). Via layout pattern 322 b is positioned between conductive feature layout pattern 316 c and metal over diffusion layout pattern 312. In comparison with via layout pattern 322 a of FIG. 3A, via layout pattern 322 b is shifted one M0 pitch P1 in a third direction (e.g., negative Y direction). For example, via layout pattern 322 b overlaps gridline 302 c, and via layout pattern 322 a of FIG. 3A overlaps gridline 302 b. Other configurations or quantities of via layout pattern 322 b are within the scope of the present disclosure.

In comparison with layout design 300A of FIG. 3A, metal over diffusion layout pattern 312 of set of metal over diffusion layout patterns 310′ of FIG. 3B replaces metal over diffusion layout patterns 310 a and 310 b of set of metal over diffusion layout patterns 310. Metal over diffusion layout pattern 312 corresponds to the metal over diffusion layout patterns 310 a and 310 b not being separated from each other in the second direction Y, thus forming a single metal over diffusion layout pattern (e.g., metal over diffusion layout pattern 312). Metal over diffusion layout pattern 312 is similar to metal over diffusion layout patterns 310 a, 310 b, and similar detailed description is therefore omitted. Metal over diffusion layout pattern 312 is usable to manufacture a corresponding contact 412 (FIG. 4B) of integrated circuit 400. Other configurations or quantities of metal over diffusion layout pattern 312 are within the scope of the present disclosure.

Signal V1 is applied to a conductive structure 416 c (FIG. 4B) manufactured by conductive feature layout pattern 316 c.

Layout designs 300A and 300B illustrate one or more design rules of methods 100-200. In some embodiments, layout design 300B incorporates at least one or more MD design rules. For example, if the same signal V1 is applied to two or more conductive feature layout patterns (e.g., conductive feature layout patterns 314 b and 314 d) in FIG. 3A, and the conductive feature layout patterns 314 b, 314 d are coupled to corresponding metal over diffusion layout patterns 310 a, 310 b by corresponding via layout patterns 322 a, 320 a that are separated from each other in the second direction Y, then the metal over diffusion layout patterns 310 a, 310 b of FIG. 3A are merged to form a single metal over diffusion layout pattern (e.g. metal over diffusion layout pattern 312), and a single M0 metal track (e.g., conductive feature layout pattern 316 c) is connected to the single metal over diffusion layout pattern (e.g. metal over diffusion layout pattern 312) as shown in FIG. 3B. In this example, as shown in FIG. 3B, a single M0 metal track (e.g., conductive feature layout pattern 316 c) is connected to the single metal over diffusion layout pattern (e.g. metal over diffusion layout pattern 312) by via layout pattern 322 b versus the dual-metal tracks M0 (e.g., conductive feature layout patterns 314 b and 314 d) as shown in FIG. 3A. In layout design 300B, routing resources are saved by reducing the use of one M0 metal track position (e.g., conductive feature layout pattern 316 b or 3160 and one via layout pattern (e.g., via layout pattern 320 a), and the saved M0 metal track position (e.g., conductive feature layout pattern 316 b or 3160 are usable for the routing of other features.

In some embodiments, the layout design 300B implementation of the MD design rule of methods 100-200 of FIGS. 1-2, results in layout design 300B utilizing a single via layout pattern (e.g., via layout pattern 322 b), a single conductive feature layout pattern (e.g., conductive feature layout pattern 316 c), and a single metal over diffusion layout pattern (e.g., metal over diffusion layout pattern 312).

FIG. 4A is a diagram of an integrated circuit 400A, in accordance with some embodiments.

Structural relationships including alignment, lengths and widths, as well as configurations of integrated circuit 400A-400B are similar to the structural relationships and configurations of layout design 300A of FIG. 3A and layout design 300B of FIG. 3B, and will not be described in FIGS. 4A-4B for brevity.

Integrated circuit 400A is manufactured by layout design 300A. In some embodiments, integrated circuit 400A corresponds to the integrated circuit after operation 106 in method 100 (FIG. 1).

Integrated circuit 400 includes gates 404 a and 404 b (collectively referred to as “set of gates 404”) extending in the second direction Y and being located on the first level of integrated circuit 400A. In some embodiments, the first level of integrated circuit 400A or 400B is referred to as the Poly level. Each of the gates of the set of gates 404 is separated from an adjacent gate of the set of gates 404 in at least the first direction X by a pitch P2 (not labelled). Gate 404 a and gate 404 b are separated from each other in the second direction Y. In some embodiments, gate 404 a and 404 b of FIG. 4A correspond to gate structures after operation 106 of method 100 of FIG. 1. Other quantities or configurations of the set of gates 404 are within the scope of the present disclosure.

Integrated circuit 400A further includes contacts 410 a, 410 b (collectively referred to as “set of contacts 410”) extending in the second direction Y and being located on the first level of integrated circuit 400A. Each of the contacts of the set of contacts 410 is separated from an adjacent contact of the set of contacts 410 in at least the first direction X. Contact 410 a and contact 410 b are separated from each other in the second direction Y. Other quantities or configurations of the set of contacts 410 are within the scope of the present disclosure.

Integrated circuit 400A further includes conductive structures 414 a, 414 b, 414 c, 414 d, 414 e, 414 f (collectively referred to as “set of conductive structures 414”) extending in the first direction X. For ease of illustration, conductive structures 414 a, 414 c, 414 e, 414 f are not shown in FIG. 4A. Set of conductive structures 414 overlaps at least the set of gates 404 or the set of contacts 410. Set of conductive structures 414 is located on a second level of integrated circuit 400. In some embodiments, the second level of integrated circuit 400A is different from the first level. In some embodiments, the second level corresponds to the M0 level of integrated circuit 400A or 400B. Conductive structure 414 b overlaps gate 404 a and contact 410 a. Conductive structure 414 d overlaps gate 404 b and contact 410 b. Each of the conductive structures of the set of conductive structures 414 is separated from an adjacent conductive structure of the set of conductive structures 414 in at least the second direction Y. Conductive structure 414 b overlaps and is aligned with gridline 302 b, conductive structure 414 d overlaps and is aligned with gridline 302 d. Other quantities or configurations of the set of conductive structures 414 are within the scope of the present disclosure.

Integrated circuit 400A further includes vias 420 a, 422 a (collectively referred to as “set of vias 420”) coupling the set of conductive structures 414 to the set of contacts 410. The set of vias 420 is between the set of conductive structures 414 and the set of contacts 410. Via 422 a is located where conductive structure 414 b overlaps contact 410 a. Via 420 a is located where conductive structure 414 d overlaps contact 410 b. Vias 420 a, 422 a are positioned at the VD level of integrated circuit 400A or 400B. Other quantities or configurations of the set of vias 420 are within the scope of the present disclosure.

Integrated circuit 400A further includes vias 430, 432 (collectively referred to as “set of vias 440”) coupling a set of power rails (not shown) to the set of gates 404. The set of vias 440 is between the set of power rails (not shown) and the set of gates 404. Via 430 is located where a first power rail (not shown) of the set of power rails overlaps gate 404 a. Via 432 is located where a second power rail (not shown) of the set of power rails overlaps gate 404 b. Vias 430, 432 are positioned at the VG level of integrated circuit 400A or 400B. Other quantities or configurations of the set of vias 440 or the set of power rails (not shown) are within the scope of the present disclosure.

Conductive structures 414 b and 414 d are each configured to receive signal V1. Conductive structure 414 b is electrically coupled to contact 410 a by via 422 a. Conductive structure 414 d is electrically coupled to contact 410 b by via 420 a. In some embodiments, contact 410 a is configured to receive signal V1 through via 422 a and conductive structure 416 b, and contact 410 b is configured to receive signal V1 through via 420 a and conductive structure 416 d. In these embodiments, contacts 410 a and 410 b are both configured to receive signal V1 (e.g., configured to be at the same voltage level).

FIG. 4B is a diagram of an integrated circuit 400B, in accordance with some embodiments.

Integrated circuit 400B is manufactured by layout design 300B. In some embodiments, integrated circuit 400B corresponds to the integrated circuit after operation 106 in method 100 (FIG. 1).

Integrated circuit 400B is a variation of integrated circuit 400A (FIG. 4A).

In comparison with integrated circuit 400A of FIG. 4A, contact 412 of FIG. 4A replaces contacts 410 a, 410 b, and similar detailed description is therefore omitted.

In comparison with integrated circuit 400A of FIG. 4A, conductive structure 416 c of FIG. 4B replaces conductive structures 414 b, 414 d, and similar detailed description is therefore omitted.

In comparison with integrated circuit 400A of FIG. 4A, via 422 b replaces vias 420 a and 422 a, and similar detailed description is therefore omitted.

Conductive structure 416 c is configured to receive signal V1. Conductive structure 416 c is electrically coupled to contact 412 by via 422 b. In some embodiments, contact 412 is configured to receive signal V1 through via 422 b and conductive structure 416 c.

Integrated circuits 400A and 400B illustrate one or more design rules of methods 100-200. In some embodiments, integrated circuit 400B incorporates at least one or more MD design rules. For example, if the same signal V1 is applied to two or more conductive structures (e.g., conductive structures 414 b and 414 d) in FIG. 4A, and the conductive structures 414 b, 414 d are coupled to corresponding contacts 410 a, 410 b by corresponding vias 422 a, 420 a, and the contacts 410 a, 410 b are separated from each other in the second direction Y, then the contacts 410 a, 410 b of FIG. 4A are merged to form a single contact (e.g., contact 412) as shown in FIG. 4B. In this example, as shown in FIG. 4B, a single M0 metal track (e.g., conductive structure 416 c) is electrically coupled to the single contact (e.g., contact 412) by via 422 b versus the dual-metal tracks M0 (e.g., conductive structures 414 b and 414 d) as shown in FIG. 4A.

In integrated circuit 400B, routing resources are saved by reducing the use of one M0 metal track position (e.g., conductive structure 414 b or 414 d) and one via (e.g., via 420 a or 422 a), and the saved M0 metal track position (e.g., conductive structure 414 b or 414 d) can be used for the routing of other features.

In some embodiments, integrated circuit 400B implements one or more of the set of design rules of methods 100-200 of FIGS. 1-2, resulting in integrated circuit 400B utilizing a single via (e.g., via 422 b), a single conductive structure (e.g., conductive structure 416 c), and a single contact (e.g., contact 412).

FIG. 5A is a diagram of a layout design 500A of an integrated circuit, in accordance with some embodiments.

Layout design 500A is usable to manufacture an integrated circuit similar to integrated circuit 400A of FIG. 4A. In some embodiments, layout design 500A corresponds to the first layout design of an integrated circuit after operation 202 in method 200 (FIG. 2).

Layout design 500A includes rail layout patterns 306 a and 306 b and set of cut feature layout patterns 308 from layout design 300A or 300B of FIGS. 3A-3B, and similar detailed description is therefore omitted.

Layout design 500A further includes a set of gate layout patterns 504, a set of metal over diffusion layout patterns 510, a set of conductive feature layout patterns 514, a set of via layout patterns 520 and a set of via layout patterns 550.

Layout design 500A is a variation of layout design 300B (FIG. 3B).

In comparison with layout design 300B of FIG. 3B, set of gate layout patterns 504 of FIG. 5A replaces set of gate layout patterns 304, and similar detailed description is therefore omitted. Set of gate layout patterns 504 includes one or more of gate layout patterns 304 a, 304 b or 504 a. Gate layout pattern 504 a is similar to gate layout pattern 304 a or 304 b, and similar detailed description is therefore omitted. Other configurations or quantities of layout patterns in the set of gate layout patterns 504 are within the scope of the present disclosure.

In comparison with layout design 300B of FIG. 3B, set of metal over diffusion layout patterns 510 of FIG. 5A replaces set of metal over diffusion layout patterns 316′, and similar detailed description is therefore omitted.

Set of metal over diffusion layout patterns 510 includes one or more of metal over diffusion layout patterns 312, 512, 513 a or 513 b. Set of metal over diffusion layout patterns 510 includes other layout patterns in FIG. 5A that are not labeled. Metal over diffusion layout pattern 512, 513 a or 513 b is similar to metal over diffusion layout pattern 312 of FIG. 3B, and similar detailed description is therefore omitted. Gate layout pattern 504 a is positioned between metal over diffusion layout pattern 512 and metal over diffusion layout pattern 312. Metal over diffusion layout pattern 513 a is positioned between gate layout pattern 304 a and gate layout pattern 304 b. Metal over diffusion layout pattern 513 b is positioned between gate layout pattern 304 a and gate layout pattern 304 b. Metal over diffusion layout pattern 513 a is separated from metal over diffusion layout pattern 513 b in the second direction Y. Other configurations or quantities of layout patterns in the set of metal over diffusion layout patterns 510 are within the scope of the present disclosure.

In comparison with layout design 300B of FIG. 3B, set of conductive feature layout patterns 514 of FIG. 5A replaces set of conductive feature layout patterns 316, and similar detailed description is therefore omitted. The set of conductive feature layout patterns 514 includes one or more of conductive feature layout patterns 514 a, 514 b, 514 c, 514 d, 514 e, 514 f or 514 g.

Conductive feature layout patterns 514 a and 514 e of FIG. 5A replace corresponding conductive feature layout patterns 316 a, 316 e of FIG. 3B, and similar detailed description is therefore omitted. Conductive feature layout pattern 514 b of FIG. 5A replaces conductive feature layout patterns 314 b, 314 f of FIG. 3B, and similar detailed description is therefore omitted. Conductive feature layout patterns 514 c and 514 f of FIG. 5A replace conductive feature layout pattern 316 c of FIG. 3B, and similar detailed description is therefore omitted. Conductive feature layout patterns 514 d and 514 g of FIG. 5A replace corresponding conductive feature layout patterns 316 d, 316 g of FIG. 3B, and similar detailed description is therefore omitted. Other configurations or quantities of layout patterns in the set of conductive feature layout patterns 514 are within the scope of the present disclosure.

Set of via layout patterns 520 includes one or more of via layout patterns 322 b or 522 a. Via layout pattern 322 b is described in FIGS. 3A-3B, and similar detailed description is therefore omitted.

Via layout pattern 522 a is similar to via layout pattern 322 b of FIG. 3B, and similar detailed description is therefore omitted. Via layout pattern 522 a is positioned between conductive feature layout pattern 514 d and metal over diffusion layout pattern 512. Via layout pattern 546 a is located where conductive feature layout pattern 514 d overlaps metal over diffusion layout pattern 512. Via layout pattern 522 a overlaps gridline 302 d. Via layout pattern 522 a is usable to manufacture a via (e.g. via 420 a, 422 a, 422 b) of an integrated circuit, such as integrated circuit 400A, 400B (FIGS. 4A-4B). Via layout pattern 522 a is positioned at the VD level of layout design 500A or 500B. Other configurations or quantities of via layout pattern 522 a are within the scope of the present disclosure.

Set of via layout patterns 550 includes one or more of via layout patterns 540 a, 542, 544 or 546 a.

Via layout pattern 540 a is similar to via layout pattern 330 or 332 of FIGS. 3A-3B, and similar detailed description is therefore omitted. Via layout pattern 540 a is positioned between conductive feature layout pattern 514 b and gate layout pattern 304 a. Via layout pattern 540 a is located where conductive feature layout pattern 514 b overlaps gate layout pattern 304 a. Via layout pattern 540 a overlaps gridline 302 b. Via layout pattern 540 a is usable to manufacture a via (e.g. via 430, 432) of an integrated circuit, such as integrated circuit 400A, 400B (FIGS. 4A-4B). Via layout pattern 540 a is positioned at the VG level of layout design 500A or 500B. Other configurations or quantities of via layout pattern 540 a are within the scope of the present disclosure.

Via layout pattern 542 is similar to via layout pattern 330 or 332 of FIGS. 3A-3B, and similar detailed description is therefore omitted. Via layout pattern 542 is positioned between conductive feature layout pattern 514 g and gate layout pattern 304 a. Via layout pattern 542 is located where conductive feature layout pattern 514 g overlaps gate layout pattern 304 a. Via layout pattern 542 overlaps gridline 302 d. Via layout pattern 542 is usable to manufacture a via (e.g. via 430, 432) of an integrated circuit, such as integrated circuit 400A, 400B (FIGS. 4A-4B). Via layout pattern 542 is positioned at the VG level of layout design 500A or 500B. Other configurations or quantities of via layout pattern 542 are within the scope of the present disclosure.

Via layout pattern 544 is similar to via layout pattern 330 or 332 of FIGS. 3A-3B, and similar detailed description is therefore omitted. Via layout pattern 544 is positioned between conductive feature layout pattern 514 a and gate layout pattern 544. Via layout pattern 544 is located where conductive feature layout pattern 514 a overlaps gate layout pattern 544. Via layout pattern 544 overlaps gridline 302 a. Via layout pattern 544 is usable to manufacture a via (e.g. via 430, 432) of an integrated circuit, such as integrated circuit 400A, 400B (FIGS. 4A-4B). Via layout pattern 544 is positioned at the VG level of layout design 500A or 500B. Other configurations or quantities of via layout pattern 544 are within the scope of the present disclosure.

Via layout pattern 546 a is similar to via layout pattern 330 or 332 of FIGS. 3A-3B, and similar detailed description is therefore omitted. Via layout pattern 546 a is positioned between conductive feature layout pattern 514 e and gate layout pattern 304 b. Via layout pattern 546 a is located where conductive feature layout pattern 514 e overlaps gate layout pattern 304 b. Via layout pattern 546 a overlaps gridline 302 a. Via layout pattern 546 a is usable to manufacture a via (e.g. via 430, 432) of an integrated circuit, such as integrated circuit 400A, 400B (FIGS. 4A-4B). Via layout pattern 546 a is positioned at the VG level of layout design 500A or 500B. Other configurations or quantities of via layout pattern 546 a are within the scope of the present disclosure.

As shown in FIG. 5A, via layout pattern 540 a is located less than one M0 metal track pitch P1 (not labelled) away from the set of cut feature layout patterns 308. Similarly, conductive feature layout pattern 514 b is located less than one M0 metal track pitch P1 (not labelled) away from the set of cut feature layout patterns 308.

In some embodiments, a layout pattern located directly next to another layout pattern corresponds to a layout pattern located less than one pitch away from the other layout pattern. In some embodiments, each of via layout pattern 540 a and conductive feature layout pattern 514 b is located directly next to the set of cut feature layout patterns 308.

In some embodiments, via layout patterns located less than one M0 metal track pitch P1 (not labelled) away from cut feature layout patterns results in process limitations.

As shown in FIG. 5A, via layout pattern 542 and via layout pattern 544 are located at least one M0 metal track pitch P1 (not labelled) away from the set of cut feature layout patterns 308. Similarly, conductive feature layout pattern 514 g and conductive feature layout pattern 514 a are located at least one M0 metal track pitch P1 (not labeled) away from the set of cut feature layout patterns 308.

FIG. 5B is a diagram of a layout design 500B of an integrated circuit, in accordance with some embodiments.

Layout design 500B is usable to manufacture an integrated circuit similar to integrated circuit 400B of FIG. 4B. In some embodiments, layout design 500B corresponds to the revised first layout design of an integrated circuit after operation 206 in method 200 (FIG. 2).

Layout design 500B is a variation of layout design 500A (FIG. 5A).

In comparison with layout design 500A of FIG. 5A, set of conductive feature layout patterns 516 of FIG. 5B replaces set of conductive feature layout patterns 514, and similar detailed description is therefore omitted. The set of conductive feature layout patterns 516 includes one or more conductive feature layout patterns 516 a, 516 b, 516 c, 516 d, 516 e, 516 f and 516 g. Conductive feature layout patterns 516 a and 516 e of FIG. 5B replace corresponding conductive feature layout patterns 514 a and 514 e of FIG. 5A, and similar detailed description is therefore omitted. Conductive feature layout pattern 516 b and 516 f of FIG. 5B replaces conductive feature layout pattern 514 b of FIG. 5A, and similar detailed description is therefore omitted. Conductive feature layout patterns 516 c of FIG. 5B replaces conductive feature layout patterns 514 c and 514 f of FIG. 5A, and similar detailed description is therefore omitted. Conductive feature layout patterns 516 d and 516 g of FIG. 5B replace corresponding conductive feature layout patterns 514 d and 514 g of FIG. 5A, and similar detailed description is therefore omitted. Other configurations or quantities of layout patterns in the set of conductive feature layout patterns 516 are within the scope of the present disclosure.

In comparison with layout design 500A of FIG. 5A, set of via layout patterns 520′ of FIG. 5B replaces set of via layout patterns 520, and similar detailed description is therefore omitted. Set of via layout patterns 520′ includes one or more of via layout patterns 522 b or 522 c.

In comparison with layout design 500A of FIG. 5A, via layout pattern 522 b of FIG. 5B replaces via layout pattern 522 a, and similar detailed description is therefore omitted. Via layout pattern 522 b is between conductive feature layout pattern 516 c and metal over diffusion layout pattern 512. Via layout pattern 522 b is positioned where conductive feature layout pattern 516 c overlaps metal over diffusion layout pattern 512. Via layout pattern 522 b overlaps gridline 302 d. Via layout pattern 522 b is positioned at the VD level of layout design 500B. Other configurations or quantities of via layout pattern 522 b are within the scope of the present disclosure.

In comparison with layout design 500A of FIG. 5A, via layout pattern 522 c of FIG. 5B replaces via layout pattern 322 b, and similar detailed description is therefore omitted. Via layout pattern 522 c is between conductive feature layout pattern 516 f and metal over diffusion layout pattern 312. Via layout pattern 522 c is positioned where conductive feature layout pattern 516 c overlaps metal over diffusion layout pattern 312. Via layout pattern 522 c overlaps gridline 302 b. Via layout pattern 522 c is positioned at the VD level of layout design 500B. Other configurations or quantities of via layout pattern 522 c are within the scope of the present disclosure.

In comparison with layout design 500A of FIG. 5A, set of via layout patterns 550′ of FIG. 5B replaces set of via layout patterns 550, and similar detailed description is therefore omitted. Set of via layout patterns 550′ includes one or more of via layout patterns 540 b, 542, 544 or 546 b.

In comparison with layout design 500A of FIG. 5A, via layout pattern 540 b of FIG. 5B replaces via layout pattern 540 a, and similar detailed description is therefore omitted. Via layout pattern 540 b is positioned between conductive feature layout pattern 516 e and gate layout pattern 304 a. Via layout pattern 540 b is positioned where conductive feature layout pattern 516 e overlaps gate layout pattern 304 a. In comparison with via layout pattern 540 a of FIG. 5A, via layout pattern 540 b is shifted one M0 pitch P1 in the second direction Y. For example, via layout pattern 540 b overlaps gridline 302 a. Via layout pattern 540 b is positioned at the VG level of layout design 500B. Other configurations or quantities of via layout pattern 540 b or set of via layout patterns 550′ are within the scope of the present disclosure.

Layout designs 500A and 500B illustrate one or more design rules of methods 100-200. In some embodiments, layout design 500B incorporates at least one or more VG landing design rules or one or more M0 spacing design rules.

In some embodiments, if one or more VG via layout patterns (e.g., via layout patterns 540 a, 542, 544 or 546 a) in FIG. 5A, are located less than one M0 metal track pitch P1 (not labelled) away from the set of cut feature layout patterns 308, then during operation 106 of method 100 of the manufacturing process of an integrated circuit, using layout design 500A, may result in a lower manufacturing yield from process limitations. For example, during operation 106 of method 100, if the removed portion of the gate structure (e.g., the gate structure portion identified by the set of cut feature layout patterns 308) is not sufficiently separated from one or more VG vias (e.g., manufactured by the VG via layout patterns), then due to process limitations, either less surface area of the remaining gate structure is available for landing (e.g., forming) the one or more VG vias or portions of the one or more VG vias may also be removed during operation 106 resulting in a lower manufacturing yield.

In some embodiments, as shown in layout design 500B of FIG. 5B, in order to overcome these process limitations, one or more VG landing design rules of methods 100-200 include shifting VG via layout patterns (e.g., via layout pattern 540 b) at least one M0 metal track position (e.g., pitch P1) away from the set of cut feature layout patterns 308 in the second direction Y, for VG via layout patterns (e.g., via layout patterns 540 a, 542, 544 or 546 a) located less than one M0 metal track pitch P1 (not labelled) away from the set of cut feature layout patterns 308.

By shifting VG via layout patterns (e.g., via layout patterns 540 b, 542, 544 or 546 b of layout design 500B) at least one M0 metal track pitch away from the set of cut feature layout patterns 308, one or more gate structures have additional VG via landing space to account for process limitations of the cut process of operation 106 of method 100. Therefore, by utilizing these one or more VG landing design rules, each of the VG via layout patterns (e.g., via layout patterns 540 b, 542, 544 or 546 b of layout design 500B) of layout design 500B is separated at least one M0 metal track pitch away from the set of cut feature layout patterns 308 as shown in FIG. 5B. In some embodiments, layout design 500B incorporates at least one or more VG landing design rules.

As shown in FIG. 5B, via layout patterns 540 b, 542 and 544 are together positioned in a right-angled VG landing configuration. In some embodiments, layout design 500B incorporates one or more M0 metal track design rules of methods 100-200. In some embodiments, one or more M0 metal track design rules of methods 100-200 include separating conductive feature layout patterns in the first direction X. In some embodiments, one or more M0 metal track design rules are implemented in conjunction with VG landing design rules.

As shown in FIG. 5B, conductive feature layout patterns 516 a and 516 e are separated from each other in the first direction X. For example, by moving via layout pattern 540 b one metal track position away from the set of cut feature layout patterns 308 in the second direction Y, and separating conductive feature layout patterns 516 a and 516 e in the first direction X, one M0 metal track position (e.g., conductive feature layout pattern 516 f) is useable for other features yielding saved routing resources.

In this example, after moving via layout pattern 540 b one metal track position away from the set of cut feature layout patterns 308, if conductive feature layout patterns 516 a and 516 e were not separated from each other in the first direction X, then gate layout patterns 304 a and 504 a would be coupled by conductive feature layout pattern 514 a. In some embodiments, separating conductive feature layout patterns 516 a and 516 e prevents gate layout patterns 304 a and 504 a from being coupled to each other, and saves routing resources.

In layout design 500B, routing resources are saved by reducing the use of one M0 metal track position (e.g., conductive feature layout pattern 514 b or 514 e) of layout design 500A, and the saved M0 metal track position (e.g., conductive feature layout pattern 516 e or 5160 of layout design 500B can be used for the routing of other features.

In some embodiments, by utilizing layout design 500B and the corresponding design rules, one or more of conductive feature layout patterns 516 a, 516 d, 516 e or 516 g is used to cross-couple the set of gate layout patterns 504 to one or more gate layout patterns of other devices (e.g., FIG. 5C). In some embodiments, set of gate layout patterns 504 is cross-coupled to one or more gate layout patterns of latches, transmission gates, multiplexers, or the like. For example, as shown in FIG. 5C, set of gate layout patterns 504 is cross-coupled to gate layout pattern 550 a.

In some embodiments, the layout design 500B implementation of the design rule of methods 100-200 of FIGS. 1-2, results in layout design 500B utilizing VG via layout patterns (e.g., via layout pattern 540 b, 542 and 544) that are separated from the set of cut feature layout patterns 308 by at least one M0 metal track position, and conductive feature layout patterns (e.g., conductive feature layout patterns 516 a and 516 e) that are separated from each other in the first direction X.

For example, if a VG via layout pattern is directly adjacent to a cut feature layout pattern, then the VG via layout pattern is moved one metal track position in the second direction or the third direction.

FIG. 5C is a diagram of a layout design 500C of an integrated circuit, in accordance with some embodiments.

Layout design 500C is usable to manufacture a portion of an integrated circuit similar to integrated circuit 400B of FIG. 4B. In some embodiments, layout design 500C corresponds to the revised first layout design of an integrated circuit after operation 206 in method 200 (FIG. 2).

Layout design 500C is a variation of layout design 500B (FIG. 5B). In comparison with layout design 500B of FIG. 5B, layout design 500C further includes layout design 500B′.

Layout design 500B′ includes a gate layout pattern 550 a and a via layout pattern 560 a. Gate layout pattern 550 a is similar to gate layout pattern 304 a, via layout pattern 560 a is similar to via layout pattern 540 b, and similar detailed description is therefore omitted.

Layout design 500B′ is cross-coupled to layout design 500B by at least conductive feature layout pattern 516 e. For example, gate layout pattern 550 a is cross-coupled to gate layout pattern 304 a by via layout pattern 560 a, via layout pattern 540 b and conductive feature layout pattern 516 e.

FIG. 6 is a diagram of a layout design 600 of an integrated circuit, in accordance with some embodiments.

Layout design 600 is usable to manufacture an integrated circuit similar to integrated circuit 400A of FIG. 4A or integrated circuit 400B of FIG. 4B.

In some embodiments, layout design 600 corresponds to the first layout design of an integrated circuit after operation 202 in method 200 (FIG. 2). In some embodiments, layout design 600 corresponds to the revised first layout design of an integrated circuit after operation 206 in method 200 (FIG. 2). In some embodiments, layout design 600 corresponds to a layout design of a standard cell 601 having a height H1 in the second direction Y.

Layout design 600 is a variation of layout design 500B (FIG. 5B).

Layout design 600 includes rail layout patterns 306 a and 306 b, and gate layout patterns 304 a, 504 a from layout design 500A or 500B of FIGS. 5A-5B, and similar detailed description is therefore omitted. Gate layout patterns 304 a and 504 a are separated from each other in the first direction X by a poly pitch P1A. Poly pitch P1A is measured from the center of gate layout patterns 304 a and 504 a.

Layout design 600 further includes active region layout patterns 602 and 604 (collectively referred to as “set of active region layout patterns 630”) extending in a first direction X. Active region layout patterns 602, 604 of the set of active region layout patterns 630 are separated from one another in the second direction Y. The set of active region layout patterns 630 is usable to manufacture a corresponding set of active regions (not shown) of integrated circuit 400A or 400B. Gate layout patterns 304 a and 504 a overlap active region layout patterns 602 and 604. In some embodiments, the set of active region layout patterns 630 is located on a third layout level. In some embodiments, the third layout level is different from the first layout level and the second layout level. In some embodiments, the third layout level corresponds to the oxide-diffusion (OD) layout level. In some embodiments, the third layout level is below the first layout level and the second level. Other configurations or quantities of active region layout patterns 602 or 604 are within the scope of the present disclosure.

Layout design 600 further includes fin layout patterns 602 a, 602 b (collectively referred to as “set of fin layout patterns 603”) each extending in the first direction X. Fin layout patterns 602 a, 602 b are over active region layout pattern 602. The set of fin layout patterns 603 are below the set of gate layout patterns 504. Each of the layout patterns of the set of fin layout patterns 603 is separated from an adjacent layout pattern of the set of fin layout patterns 603 in the second direction Y by a fin pitch P2A. Fin layout patterns 602 a and 602 b are separated from each other in the second direction Y by the fin pitch P2A. In some embodiments, fin pitch P2A is measured from the center of fin layout patterns 602 a and 602 b. The set of fin layout patterns 603 is usable to manufacture a corresponding set of fins (not shown) of integrated circuit 400A or 400B. Other configurations or quantities of layout patterns in the set of fin layout patterns 603 are within the scope of the present disclosure.

Layout design 600 further includes fin layout patterns 604 a, 604 b (collectively referred to as “set of fin layout patterns 605”) each extending in the first direction X. Fin layout patterns 604 a, 604 b are over active region layout pattern 604. The set of fin layout patterns 605 are below the set of gate layout patterns 504. Each of the layout patterns of the set of fin layout patterns 605 is separated from an adjacent layout pattern of the set of fin layout patterns 605 in the second direction Y by the fin pitch P2A. Fin layout patterns 604 a and 604 b are separated from each other in the second direction Y by the fin pitch P2A. In some embodiments, fin pitch P2A is measured from the center of fin layout patterns 604 a and 604 b. The set of fin layout patterns 605 is usable to manufacture a corresponding set of fins (not shown) of integrated circuit 400A or 400B. Other configurations or quantities of layout patterns in the set of fin layout patterns 605 are within the scope of the present disclosure.

Layout design 600 further includes cut feature layout patterns 608 a, 608 b, 608 c, and 608 d (collectively referred to as a “set of cut feature layout patterns 608”) extending in the first direction X. In some embodiments, one or more cut feature layout patterns of the set of cut feature layout pattern 608 is separated from each other in at least the second direction Y. One or more cut feature layout patterns of the set of cut feature layout pattern 608 is similar to one or more cut feature layout patterns of the set of cut feature layout patterns 308, and similar detailed description is therefore omitted.

Cut feature layout pattern 608 a and cut feature layout pattern 608 b are positioned between gridlines 302 b and 302 c.

Cut feature layout pattern 608 c includes one or more cut feature layout patterns. Cut feature layout pattern 608 c overlaps a first side of standard cell 601.

Cut feature layout pattern 608 d includes one or more cut feature layout patterns. Cut feature layout pattern 608 d overlaps a second side of standard cell 601. The first side of standard cell 601 is on an opposite side of standard cell 601 from the second side of standard cell 601. Other configurations or quantities of cut feature layout patterns in the set of cut feature layout patterns 608 are within the scope of the present disclosure.

Layout design 600 further includes metal over diffusion layout patterns 610, 612, 614 a, 614 b (collectively referred to as a “set of metal over diffusion layout patterns 614”). Set of metal over diffusion layout patterns 614 of layout design 600 is similar to the set of metal over diffusion layout patterns 510 of layout designs 500A-500B of FIGS. 5A-5B, and similar detailed description is therefore omitted. Metal over diffusion layout patterns 610, 612, 614 a, 614 b are similar to corresponding metal over diffusion layout patterns 510, 512, 513 a, 513 b of FIGS. 5A-5B, and similar detailed description is therefore omitted. Metal over diffusion layout patterns 614 a and 614 b are positioned next to gate layout pattern 304 a. Metal over diffusion layout patterns 614 a and 614 b are separated from each other in the second direction Y. Metal over diffusion layout patterns 614 a and 614 b overlap corresponding active region layout patterns 602 and 604. Other configurations or quantities of layout patterns in the set of metal over diffusion layout patterns 614 are within the scope of the present disclosure.

Layout design 600 further includes one or more conductive feature layout patterns 616 a, . . . , 616 g (collectively referred to as a “set of conductive feature layout patterns 616”). Set of conductive feature layout patterns 616 is similar to the set of conductive feature layout patterns 516 of FIG. 5B, and similar detailed description is therefore omitted. Other configurations or quantities of layout patterns in the set of conductive feature layout patterns 616 are within the scope of the present disclosure.

Layout design 600 further includes one or more via layout patterns 642 a, 642 b, 642 c and 642 d (collectively referred to as a “set of via layout patterns 642”).

Via layout patterns 642 a, 642 d, 642 c are similar to corresponding via layout patterns 542, 540 b, 544 of layout design 500B of FIG. 5B, and similar detailed description is therefore omitted. Via layout pattern 642 b is similar to one or more of via layout patterns 542, 540 b, 544 of layout design 500B of FIG. 5B, and similar detailed description is therefore omitted.

Via layout pattern 642 a is positioned between conductive feature layout pattern 616 g and gate layout pattern 304 a. Via layout pattern 642 a is positioned where conductive feature layout pattern 616 g overlaps gate layout pattern 304 a.

Via layout pattern 642 b is positioned between conductive feature layout pattern 616 d (not labelled) and gate layout pattern 504 a. Via layout pattern 642 b is positioned where conductive feature layout pattern 616 d (not labelled) overlaps gate layout pattern 504 a.

Via layout pattern 642 c is positioned between conductive feature layout pattern 616 a and gate layout pattern 504 a. Via layout pattern 642 c is positioned where conductive feature layout pattern 616 a overlaps gate layout pattern 504 a.

Via layout pattern 642 d is positioned between conductive feature layout pattern 616 e (not labelled) and gate layout pattern 304 a. Via layout pattern 642 d is positioned where conductive feature layout pattern 616 e (not labelled) overlaps gate layout pattern 304 a. Other configurations or quantities of one or via layout patterns of the set of via layout patterns 642 are within the scope of the present disclosure.

Via layout pattern 642 a and via layout pattern 642 d are separated from each other in the second direction Y by a distance DVG_VA. Via layout pattern 642 b and via layout pattern 642 c are separated from each other in the second direction Y by distance DVG_VA. In some embodiments, distance DVG_VA is measured from the center of via layout pattern 642 a or 642 b and corresponding via layout pattern 642 d or 642 c.

Via layout pattern 642 a and via layout pattern 642 b are separated from each other in the second direction Y by a distance DVG_HA. Via layout pattern 642 c and via layout pattern 642 d are separated from each other in the second direction Y by distance DVG_HA. In some embodiments, distance DVG_HA is measured from the center of via layout pattern 642 a or 642 c and corresponding via layout pattern 642 b or 642 d.

Each of the via layout patterns of the set of via layout patterns 642 is separated from the set of cut feature layout patterns 608 in the second direction Y by a distance S1A. For example, via layout pattern 642 c or 642 b is separated in the second direction Y from cut feature layout pattern 608 a by distance S1A. Similarly, via layout pattern 642 a or 642 d is separated in the second direction Y from cut feature layout pattern 608 b by distance S1A. In some embodiments, distance S1A is measured from the edge of via layout pattern 642 c or 642 b and the edge of cut feature layout pattern 608 a. In some embodiments, distance S1A is measured from the edge of via layout pattern 642 a or 642 d and the edge of cut feature layout pattern 608 b.

The set of active region layout patterns 630 are separated from the set of cut feature layout patterns 608 in the second direction Y by a distance S2A. For example, active region layout pattern 604 is separated from cut feature layout pattern 608 a or 608 b in the second direction Y by distance S2A. Similarly, active region layout pattern 602 is separated from cut feature layout pattern 608 a or 608 b in the second direction Y by distance S2A. In some embodiments, distance S2A is measured from an edge of active region layout pattern 604 and the edge of cut feature layout pattern 608 a or 608 b. In some embodiments, distance S2A is measured from an edge of active region layout pattern 602 and the edge of cut feature layout pattern 608 a or 608 b.

Active region layout pattern 602 and active region 604 are separated from each other in the second direction Y by a distance S3A. In some embodiments, distance S3A is measured from the edge of active region layout pattern 602 and the edge of active region layout pattern 604.

In some embodiments, a relationship between distance S3A and fin pitch P2A is expressed by formula 1: S3A≤2.5*P2A  (1)

In some embodiments, formula 1 corresponds to a relationship between the distance (e.g., S3A) between the active region layout patterns and the fin pitch (e.g., P2A) of the active region layout patterns.

In some embodiments, a relationship between distance S1A and distance S3A is expressed by formula 2: S1A≥0.3*S3A  (2)

In some embodiments, formula 2 corresponds to a relationship between the VG distance (e.g., S1A) between the set of via layout patterns 642 and the set of cut feature layout patterns 608, and the distance (e.g., S3A) between the active region layout patterns 602 and 604.

In some embodiments, a relationship between distance S2A and distance S3A is expressed by formula 3: S2A≥0.2*S3A  (3)

In some embodiments, formula 3 corresponds to a relationship between the set of cut feature layout patterns 608 and the set of active region layout patterns 630. In some embodiments, layout designs (e.g., layout design 600) that satisfy formula 3 result in the set of cut feature layout patterns 608 being sufficiently separated from the set of active region layout patterns 630 in order to overcome process limitations attributed to operation 106 of method 100.

In some embodiments, a relationship between distance DVG_HA and poly pitch P1A is expressed by formula 4: 1.1*P1A≥DVG_HA≥0.9*P1A  (4)

In some embodiments, formula 4 corresponds to a minimum and maximum distance relationship between gate layout patterns 304 a and 504 a in the first direction X. In some embodiments, formula 4 corresponds to a minimum and maximum distance relationship between VG via layout patterns (e.g., set of via layout patterns 642) in the first direction X.

In some embodiments, a relationship between distance S3A and distance DVG_HA is expressed by formula 5: 1.5*S3A≥DVG_VA≥0.8*S3A  (5)

In some embodiments, formula 5 corresponds to a minimum and maximum distance relationship between VG via layout patterns (e.g., set of via layout patterns 642) in the second direction Y.

In some embodiments, layout designs (e.g., layout design 600) that satisfy formulas 2 and 5 result in the set of via layout patterns 642 being sufficiently separated from the set of cut feature layout pattern 608 in order to overcome process limitations attributed to operation 106 of method 100.

In some embodiments, formulas 1-5 correspond to one or more design rules of layout design 600 and methods 100-200 of FIGS. 1-2. In some embodiments, layout designs that satisfy the one or more design rules specified by formulas 1-5 result in layout designs (e.g., layout design 600) which account for process limitations, and are capable of being used to consistently manufacture corresponding integrated circuits by semiconductor fabrication processes, such as methods 100-200 of FIGS. 1-2.

FIG. 7 is a diagram of a layout design 700 of an integrated circuit, in accordance with some embodiments.

Layout design 700 is usable to manufacture an integrated circuit similar to integrated circuit 400A of FIG. 4A or integrated circuit 400B of FIG. 4B.

In some embodiments, layout design 700 corresponds to the first layout design of an integrated circuit after operation 202 in method 200 (FIG. 2). In some embodiments, layout design 700 corresponds to the revised first layout design of an integrated circuit after operation 206 in method 200 (FIG. 2). In some embodiments, layout design 700 corresponds to a layout design of a standard cell 701 having a height H2 in the second direction Y.

Layout design 700 is a variation of layout design 500B of FIG. 5B or layout design 600 of FIG. 6.

Layout design 700 includes rail layout patterns 306 a and 306 b, and gate layout patterns 304 a from layout design 500A or 500B of FIGS. 5A-5B, and similar detailed description is therefore omitted.

Layout design 700 further includes gate layout patterns 704 a and 704 b. Gate layout pattern 704 a, 704 b are similar to gate layout pattern 304 b of FIG. 6, and similar detailed description is therefore omitted. Gate layout patterns 704 a, 704 b overlap active region layout patterns 602 and 604. Gate layout pattern 704 b is between gate layout patterns 304 a and 704 a. Other configurations or quantities of gate layout patterns 304 a, 704 a or 704 b are within the scope of the present disclosure.

Adjacent gate layout patterns of gate layout patterns 304 a, 704 a and 704 b are separated from each other in the first direction X by a poly pitch P1B. Poly pitch P1B is measured from the center of gate layout patterns 304 a, 704 a and 704 b.

Layout design 700 further includes active region layout patterns 602 and 604, fin layout patterns 602 a and 602 b, fin layout patterns 604 a and 604 b of layout design 600 of FIG. 6, and similar detailed description is therefore omitted. Other configurations or quantities of active region layout patterns 602 a or 602 b, or fin layout patterns 602 a, 602 b, 604 a or 604 b are within the scope of the present disclosure.

Layout design 700 further includes cut feature layout patterns 708 a, 708 b, 608 c, and 608 d (collectively referred to as a “set of cut feature layout patterns 708”) extending in the first direction X. In some embodiments, one or more cut feature layout patterns of the set of cut feature layout pattern 708 is separated from each other in at least the second direction Y. One or more cut feature layout patterns of the set of cut feature layout pattern 708 is similar to one or more cut feature layout patterns of the set of cut feature layout patterns 308 or 608, and similar detailed description is therefore omitted.

Cut feature layout patterns 708 a and 708 b are similar to corresponding cut feature layout patterns 608 a and 608 b, and similar detailed description is therefore omitted. Cut feature layout pattern 708 a and cut feature layout pattern 708 b are separated from each other in the first direction X. Cut feature layout patterns 708 b and 708 a overlap corresponding gate layout patterns 304 a and 704 a. Other configurations or quantities of cut feature layout patterns in the set of cut feature layout patterns 708 are within the scope of the present disclosure.

Layout design 700 further includes metal over diffusion layout patterns 612, 710, 712 (collectively referred to as a “set of metal over diffusion layout patterns 714”).

Set of metal over diffusion layout patterns 714 of layout design 700 is similar to the set of metal over diffusion layout patterns 510 of FIGS. 5A-5B or set of metal over diffusion layout patterns 614 of FIG. 6, and similar detailed description is therefore omitted. Metal over diffusion layout patterns 710, 712 are similar to corresponding metal over diffusion layout patterns 513 a, 513 b of FIGS. 5A-5B, and similar detailed description is therefore omitted. Metal over diffusion layout patterns 710 and 712 are positioned between gate layout patterns 704 b, 704 a. Metal over diffusion layout patterns 710 and 712 are separated from each other in the second direction Y. Metal over diffusion layout patterns 710 and 712 overlap corresponding active region layout patterns 602 and 604. Other configurations or quantities of layout patterns in the set of metal over diffusion layout patterns 714 are within the scope of the present disclosure.

Layout design 700 further includes one or more conductive feature layout patterns 716 a, . . . , 716 e (collectively referred to as a “set of conductive feature layout patterns 716”).

Set of conductive feature layout patterns 716 is similar to the set of conductive feature layout patterns 516 of FIG. 5B, and similar detailed description is therefore omitted. Other configurations or quantities of layout patterns in the set of conductive feature layout patterns 716 are within the scope of the present disclosure.

Layout design 700 further includes one or more via layout patterns 642 a, 642 d and 742 b (collectively referred to as a “set of via layout patterns 742”). Via layout pattern 742 b is similar to via layout pattern 642 b of layout design 600 of FIG. 6, and similar detailed description is therefore omitted.

Via layout pattern 642 a of layout design 700 is positioned between conductive feature layout pattern 716 e and gate layout pattern 304 a. Via layout pattern 642 a of layout design 700 is positioned where conductive feature layout pattern 716 e overlaps gate layout pattern 304 a.

Via layout pattern 642 d of layout design 700 is positioned between conductive feature layout pattern 716 a and gate layout pattern 304 a. Via layout pattern 642 d of layout design 700 is positioned where conductive feature layout pattern 716 a overlaps gate layout pattern 304 a.

Via layout pattern 742 b is positioned between conductive feature layout pattern 716 d (not labelled) and gate layout pattern 704 a. Via layout pattern 742 b is positioned where conductive feature layout pattern 716 d (not labelled) overlaps gate layout pattern 704 a. Other configurations or quantities of one or via layout patterns of the set of via layout patterns 742 are within the scope of the present disclosure.

In layout design 700, via layout pattern 642 a and via layout pattern 642 d are separated from each other in the second direction Y by a distance DVG_VB. In some embodiments, distance DVG_VB is measured from the center of via layout pattern 642 a and via layout pattern 642 d.

Via layout pattern 642 a and via layout pattern 742 b are separated from each other in the second direction Y by a distance DVG_HB. In some embodiments, distance DVG_HB is measured from the center of via layout pattern 642 a and via layout pattern 742 b.

Each of the via layout patterns of the set of via layout patterns 742 is separated from the set of cut feature layout patterns 708 in the second direction Y by a distance S1B. For example, via layout pattern 742 b is separated in the second direction Y from cut feature layout pattern 708 a by distance S1A (not labelled). Similarly, via layout pattern 642 a or 642 d is separated in the second direction Y from cut feature layout pattern 708 b by distance S1B. In some embodiments, distance S1B is measured from the edge of via layout pattern 742 b and the edge of cut feature layout pattern 708 a. In some embodiments, distance S1B is measured from the edge of via layout pattern 642 a or 642 d and the edge of cut feature layout pattern 708 b.

The set of active region layout patterns 630 are separated from the set of cut feature layout patterns 708 in the second direction Y by a distance S2B. For example, active region layout pattern 604 is separated from cut feature layout pattern 708 a or 708 b in the second direction Y by distance S2B. Similarly, active region layout pattern 602 is separated from cut feature layout pattern 708 a or 708 b in the second direction Y by distance S2B. In some embodiments, distance S2B is measured from an edge of active region layout pattern 604 and the edge of cut feature layout pattern 708 a or 708 b. In some embodiments, distance S2B is measured from an edge of active region layout pattern 602 and the edge of cut feature layout pattern 708 a or 708 b.

Active region layout pattern 602 and active region 604 are separated from each other in the second direction Y by a distance S3A. In some embodiments, distance S3A is measured from the edge of active region layout pattern 602 and the edge of active region layout pattern 604.

In some embodiments, a relationship between distance S3A and fin pitch P2A is expressed by formula 6: S3A≤2.5*P2A  (6)

In some embodiments, formula 6 corresponds to a relationship between the distance (e.g., S3A) between the active region layout patterns and the fin pitch (e.g., P2A) of the active region layout patterns.

In some embodiments, a relationship between distance S1B and distance S3A is expressed by formula 7: S1B≥0.3*S3A  (7)

In some embodiments, formula 7 corresponds to a relationship between the VG distance (e.g., S1B) between the set of via layout patterns 742 and the set of cut feature layout patterns 708, and the distance (e.g., S3A) between the active region layout patterns 602 and 604.

In some embodiments, a relationship between distance S2B and distance S3A is expressed by formula 8: S2B≥0.2*S3A  (8)

In some embodiments, formula 8 corresponds to a relationship between the set of cut feature layout patterns 708 and the set of active region layout patterns 630. In some embodiments, layout designs (e.g., layout design 700) that satisfy formula 8 results in the set of cut feature layout patterns 708 being sufficiently separated from the set of active region layout patterns 630 in order to overcome process limitations attributed to operation 106 of method 100.

In some embodiments, a relationship between distance DVG_HB and poly pitch P1B is expressed by formula 9: 2.2*P1B≥DVG_HB≥0.9*P1B  (9)

In some embodiments, formula 9 corresponds to a minimum and maximum distance relationship between adjacent gate layout patterns 304 a, 704 a and 704 b in the first direction X. In some embodiments, formula 9 corresponds to a minimum and maximum distance relationship between VG via layout patterns (e.g., set of via layout patterns 742) in the first direction X.

In some embodiments, a relationship between distance S3A and distance DVG_HB is expressed by formula 10: 1.5*S3A≥DVG_VB≥0.8*S3A  (10)

In some embodiments, formula 10 corresponds to a minimum and maximum distance relationship between VG via layout patterns (e.g., set of via layout patterns 742) in the second direction Y.

In some embodiments, layout designs (e.g., layout design 700) that satisfy formulas 7 and 10 results in the set of via layout patterns 742 being sufficiently separated from the set of cut feature layout patterns 708 in order to overcome process limitations attributed to operation 106 of method 100.

In some embodiments, formulas 6-10 correspond to one or more design rules of layout design 700 and methods 100-200 of FIGS. 1-2. In some embodiments, layout designs that satisfy the one or more design rules specified by formulas 6-10 results in layout designs (e.g., layout design 700) which account for process limitations, and are capable of being used to consistently manufacture corresponding integrated circuits by semiconductor fabrication processes, such as methods 100-200 of FIGS. 1-2.

FIG. 8 is a diagram of a layout design 800 of an integrated circuit, in accordance with some embodiments.

Layout design 800 is usable to manufacture an integrated circuit similar to integrated circuit 400A of FIG. 4A or integrated circuit 400B of FIG. 4B.

In some embodiments, layout design 800 corresponds to the first layout design of an integrated circuit after operation 202 in method 200 (FIG. 2). In some embodiments, layout design 800 corresponds to the revised first layout design of an integrated circuit after operation 206 in method 200 (FIG. 2). In some embodiments, layout design 800 corresponds to a layout design of a standard cell 870 having a height H3 in the second direction Y. In some embodiments, height H3 is twice the height H1 of standard cell 601. In some embodiments, height H3 is twice the height H2 of standard cell 701.

Layout design 800 is a variation of layout design 500B of FIG. 5B or layout design 600 of FIG. 6.

Layout design 800 includes a layout design 801A and a layout design 801B. Layout design 801A and layout design 801B are directly next to each other.

Layout design 801A is similar to layout design 600 of FIG. 6, and similar detailed description is therefore omitted.

In some embodiments, formulas 1-5, described with reference to layout design 600 of FIG. 6, are also applicable to layout design 801A, and similar detailed description is therefore omitted. In some embodiments, layout design 801A satisfies formulas 1-5 which corresponds to one or more design rules of layout design 800.

In comparison with layout design 600 of FIG. 6, set of cut feature layout patterns 608′ of layout design 801A of FIG. 8 replaces set of cut feature layout patterns 608, and similar detailed description is therefore omitted. Set of cut feature layout patterns 608′ includes one or more layout patterns of cut feature layout patterns 608 a, 608 b, 608 c, 808 e or 808 f.

In comparison with layout design 600 of FIG. 6, cut feature layout patterns 808 e and 808 f of layout design 801A of FIG. 8 replace cut feature layout patterns 608 d, and similar detailed description is therefore omitted. Cut feature layout patterns 808 e and 808 f are separated from each other in the first direction X. Cut feature layout patterns 808 e and 808 f overlap power rail layout pattern 306 b.

In comparison with layout design 600 of FIG. 6, layout design 801A does not include via layout pattern 642 c.

In comparison with layout design 600 of FIG. 6, gate layout patterns 304 a and 504 a of FIG. 8 extend in the first direction X across each of layout designs 801A and 801B.

In some embodiments, layout design 801B is a counter image of layout design 801A. In some embodiments a counter image of a layout corresponds to a rotated, mirror image of the layout. For example, in some embodiments, layout design 801B is a rotated, mirror image of layout design 801A.

Layout design 801B includes rail layout pattern 806 b. Rail layout pattern 806 b is similar to rail layout pattern 306 a of layout design 500A or 500B of FIGS. 5A-5B, and similar detailed description is therefore omitted. Rail layout pattern 806B is positioned over a side of standard cell 870 opposite from the side of standard cell 870 that is overlapped by rail layout pattern 306 a. Other configurations or quantities of rail layout patterns 306 a, 306 b or 806 b are within the scope of the present disclosure.

Layout design 801B further includes active region layout patterns 802 and 804 (collectively referred to as “set of active region layout patterns 830”) extend in the first direction X. Active region layout patterns 802 and 804 are similar to corresponding active region layout patterns 602 and 604, and similar detailed description is therefore omitted. Active region layout patterns 802 and 804 are separated from active region layout patterns 602 and 604 in the second direction Y. Gate layout patterns 304 a and 504 a overlap active region layout patterns 802 and 804. Other configurations or quantities of active region layout patterns 802 or 804 are within the scope of the present disclosure.

Layout design 801B further includes fin layout patterns 802 a, 802 b (collectively referred to as “set of fin layout patterns 803”) each extending in the first direction X. Fin layout patterns 802 a, 802 b are over active region layout pattern 802. The set of fin layout patterns 803 are similar to the set of fin layout patterns 603 of FIG. 6 and similar detailed description is therefore omitted.

Layout design 801B further includes fin layout patterns 804 a, 804 b (collectively referred to as “set of fin layout patterns 805”) each extending in the first direction X. Fin layout patterns 804 a, 804 b are over active region layout pattern 804. The set of fin layout patterns 805 are similar to the set of fin layout patterns 605 of FIG. 6 and similar detailed description is therefore omitted.

Each of the layout patterns of the set of fin layout patterns 803 or 805 is separated from an adjacent layout pattern of the corresponding set of fin layout patterns 803 or 805 in the second direction Y by a fin pitch P2C. Fin layout pattern 802 a, 804 a is separated from corresponding fin layout pattern 802 b, 804 b in the second direction Y by the fin pitch P2C. In some embodiments, fin pitch P2C is measured from the center of fin layout pattern 802 a, 804 a to the center of corresponding fin layout patterns 802 b, 804 b. Other configurations or quantities of layout patterns in the set of fin layout patterns 803 or 805 are within the scope of the present disclosure.

Layout design 801B further includes cut feature layout patterns 808 a, 808 b and 808 d (collectively referred to as a “set of cut feature layout patterns 808”) extending in the first direction X. In some embodiments, one or more cut feature layout patterns of the set of cut feature layout pattern 808 is separated from each other in at least the second direction Y. One or more cut feature layout patterns of the set of cut feature layout pattern 808 is similar to one or more cut feature layout patterns of the set of cut feature layout patterns 308, and similar detailed description is therefore omitted.

Cut feature layout pattern 808 a and cut feature layout pattern 808 b are positioned between gridlines 302 b′ and 302 c′.

Cut feature layout pattern 808 d includes one or more cut feature layout patterns. Cut feature layout pattern 808 d is similar to cut feature layout pattern 608 d of FIG. 6, and similar detailed description is therefore omitted.

Cut feature layout pattern 808 d overlaps a first side of standard cell 870. Other configurations or quantities of cut feature layout patterns in the set of cut feature layout patterns 808 are within the scope of the present disclosure.

Layout design 801B further includes metal over diffusion layout patterns 810, 812, 814 a, 814 b (collectively referred to as a “set of metal over diffusion layout patterns 814”). Set of metal over diffusion layout patterns 814 of layout design 801B is similar to the set of metal over diffusion layout patterns 510 of layout designs 500A-500B of FIGS. 5A-5B or set of metal over diffusion layout patterns 614 of FIG. 6, and similar detailed description is therefore omitted. Metal over diffusion layout patterns 810, 812, 814 a, 814 b are similar to corresponding metal over diffusion layout patterns 510, 512, 513 a, 513 b of FIGS. 5A-5B, and similar detailed description is therefore omitted. Metal over diffusion layout patterns 814 a and 814 b are positioned next to gate layout pattern 504 a. Metal over diffusion layout patterns 814 a and 814 b are separated from each other in the second direction Y. Metal over diffusion layout patterns 814 a and 814 b overlap corresponding active region layout patterns 802 and 804. Other configurations or quantities of layout patterns in the set of metal over diffusion layout patterns 814 are within the scope of the present disclosure.

Layout design 801B further includes one or more conductive feature layout patterns 816 a, . . . , 816 g (collectively referred to as a “set of conductive feature layout patterns 816”). Set of conductive feature layout patterns 816 is similar to the set of conductive feature layout patterns 516 of FIG. 5B, and similar detailed description is therefore omitted.

Conductive feature layout pattern 816 a overlaps gridlines 302 a′. Conductive feature layout pattern 816 b (not labeled) overlaps gridlines 302 b′. Conductive feature layout patterns 816 c (not labeled) and 816 e (not labeled) overlap gridline 302 c′. Conductive feature layout patterns 816 d (not labeled) and 816 f overlap gridline 302 d′. Gridlines 302 a′, 302 b′, 302 c′, 302 d′ (collectively referred to as a “set of gridlines 302”) are similar to the set of gridlines 302, and similar detailed description is therefore omitted. Other configurations or quantities of layout patterns in the set of conductive feature layout patterns 816 are within the scope of the present disclosure.

Layout design 801B further includes one or more via layout patterns 842 a, 842 c and 842 d (collectively referred to as a “set of via layout patterns 842”).

Via layout patterns 842 a, 842 d, 842 c are similar to corresponding via layout patterns 542, 540 b, 544 of layout design 500B of FIG. 5B, and similar detailed description is therefore omitted.

Via layout pattern 842 a is positioned between conductive feature layout pattern 816 g and gate layout pattern 504 a. Via layout pattern 842 a is positioned where conductive feature layout pattern 816 d (not labeled) overlaps gate layout pattern 504 a.

Via layout pattern 842 c is positioned between conductive feature layout pattern 816 a and gate layout pattern 504 a. Via layout pattern 842 c is positioned where conductive feature layout pattern 816 a overlaps gate layout pattern 504 a.

Via layout pattern 842 d is positioned between conductive feature layout pattern 816 f (not labelled) and gate layout pattern 304 a. Via layout pattern 842 d is positioned where conductive feature layout pattern 816 f (not labelled) overlaps gate layout pattern 304 a. Other configurations or quantities of one or via layout patterns of the set of via layout patterns 842 are within the scope of the present disclosure.

Via layout pattern 842 a and via layout pattern 842 d are separated from each other in the second direction Y by a distance DVG_VC1. In some embodiments, distance DVG_VC1 is measured from the center of via layout pattern 842 a and via layout pattern 842 d.

Via layout pattern 642 c and via layout pattern 842 d are separated from each other in the second direction Y by a distance DVG_VC2. In some embodiments, distance DVG_VC2 is measured from the center of via layout pattern 642 c and via layout pattern 842 d. Via layout pattern 642 a and via layout pattern 842 c are separated from each other in the second direction Y by a distance DVG_VC2. In some embodiments, distance DVG_VC2 is measured from the center of via layout pattern 642 a and via layout pattern 842 c.

Via layout pattern 842 a and via layout pattern 842 c are separated from each other in the second direction Y by a distance DVG_HC. In some embodiments, distance DVG_HC is measured from the center of via layout pattern 842 a and via layout pattern 842 c.

Each of the via layout patterns of the set of via layout patterns 842 is separated from the set of cut feature layout patterns 808 in the second direction Y by a distance S1C. For example, via layout pattern 842 c is separated in the second direction Y from cut feature layout pattern 808 b by distance S1C. Similarly, via layout pattern 842 a or 842 d is separated in the second direction Y from cut feature layout pattern 808 a by distance S1C. In some embodiments, distance S1C is measured from the edge of via layout pattern 842 a or 842 d and the edge of cut feature layout pattern 808 a. In some embodiments, distance S1A is measured from the edge of via layout pattern 842 c and the edge of cut feature layout pattern 808 b.

The set of active region layout patterns 830 are separated from the set of cut feature layout patterns 808 in the second direction Y by a distance S2C. For example, active region layout pattern 804 is separated from cut feature layout pattern 808 a, 808 d or 808 b in the second direction Y by distance S2C. Similarly, active region layout pattern 802 is separated from cut feature layout pattern 808 a, 808 d or 808 b in the second direction Y by distance S2C. In some embodiments, distance S2C is measured from an edge of active region layout pattern 804 and the edge of cut feature layout pattern 808 a, 808 d or 808 b. In some embodiments, distance S2C is measured from an edge of active region layout pattern 802 and the edge of cut feature layout pattern 808 a, 808 d or 808 b.

Active region layout pattern 802 and active region 804 are separated from each other in the second direction Y by a distance S3C. In some embodiments, distance S3C is measured from the edge of active region layout pattern 802 and the edge of active region layout pattern 804.

In some embodiments, a relationship between distance S3C and fin pitch P2C is expressed by formula 11: S3C≤2.5*P2C  (11)

In some embodiments, formula 11 corresponds to a relationship between the distance (e.g., S3C) between the active region layout patterns and the fin pitch (e.g., P2C) of the active region layout patterns.

In some embodiments, a relationship between distance S1C and distance S3C is expressed by formula 12: S1C≥0.3*S3C  (12)

In some embodiments, formula 12 corresponds to a relationship between the VG distance (e.g., S1C) between the set of via layout patterns 842 and the set of cut feature layout patterns 808, and the distance (e.g., S3C) between the active region layout patterns 802 and 804.

In some embodiments, a relationship between distance S2C and distance S3C is expressed by formula 13: S2C≥0.2*S3C  (13)

In some embodiments, formula 13 corresponds to a relationship between the set of cut feature layout patterns 808 and the set of active region layout patterns 830. In some embodiments, layout designs (e.g., layout design 800) that satisfy formula 13 results in the set of cut feature layout patterns 808 being sufficiently separated from the set of active region layout patterns 830 in order to overcome process limitations attributed to operation 106 of method 100.

In some embodiments, a relationship between distance DVG_HC and poly pitch P1C is expressed by formula 14: 1.1*P1C≥DVG_HC≥0.9*P1C  (14)

In some embodiments, formula 14 corresponds to a minimum and maximum distance relationship between gate layout patterns 304 a and 504 a in the first direction X. In some embodiments, formula 14 corresponds to a minimum and maximum distance relationship between VG via layout patterns (e.g., set of via layout patterns 842) in the first direction X.

In some embodiments, a relationship between distance S3C and distance DVG_VC1 is expressed by formula 15: 1.5*S3C≥DVG_VC1≥0.8*S3C  (15)

In some embodiments, formula 15 corresponds to a minimum and maximum distance relationship between VG via layout patterns (e.g., set of via layout patterns 842) in the second direction Y.

In some embodiments, a relationship between distance S3C and distance DVG_VC2 is expressed by formula 16: 3.6*S3C≥DVG_VC2≥2.3*S3C  (16)

In some embodiments, formula 16 corresponds to a minimum and maximum distance relationship between VG via layout patterns (e.g., set of via layout patterns 642 and 842) in the second direction Y.

In some embodiments, layout designs (e.g., layout design 800) that satisfy formulas 12 and 15 results in the set of via layout patterns 842 being sufficiently separated from the set of cut feature layout pattern 808 in order to overcome process limitations attributed to operation 106 of method 100.

In some embodiments, formulas 1-5 and 11-16 correspond to one or more design rules of layout design 800 and methods 100-200 of FIGS. 1-2. In some embodiments, formulas 1-5 correspond to one or more design rules of layout design 801A, and formulas 11-16 correspond to one or more design rules of layout design 801B.

In some embodiments, layout designs that satisfy the one or more design rules specified by formulas 1-5 and 11-16 results in layout designs (e.g., layout design 800) which account for process limitations, and are capable of being used to consistently manufacture corresponding integrated circuits by semiconductor fabrication processes, such as methods 100-200 of FIGS. 1-2.

FIG. 9 is a diagram of a layout design 900 of an integrated circuit, in accordance with some embodiments.

Layout design 900 is usable to manufacture an integrated circuit similar to integrated circuit 400A of FIG. 4A or integrated circuit 400B of FIG. 4B.

In some embodiments, layout design 900 corresponds to the first layout design of an integrated circuit after operation 202 in method 200 (FIG. 2). In some embodiments, layout design 900 corresponds to the revised first layout design of an integrated circuit after operation 206 in method 200 (FIG. 2). In some embodiments, layout design 900 corresponds to a layout design of a standard cell 970 having a height H4 in the second direction Y. In some embodiments, height H4 is twice the height H1 of standard cell 601. In some embodiments, height H4 is twice the height H2 of standard cell 701. In some embodiments, height H4 is the same as height H3.

Layout design 900 is a variation of layout design 800 of FIG. 8.

In comparison with layout design 800 of FIG. 8, layout design 900 does not include elements of layout design 800 positioned between gridlines 880 and 882.

In some embodiments, formulas 1-5, described with reference to layout design 600 of FIG. 6, are also applicable to layout design 801A, and similar detailed description is therefore omitted. In some embodiments, layout design 801A satisfies formulas 1-5 which corresponds to one or more design rules of layout design 800.

In comparison with layout design 800 of FIG. 8, set of cut feature layout patterns 908′ of layout design 900 replace set of cut feature layout patterns 608′, and similar detailed description is therefore omitted. Set of cut feature layout patterns 908′ includes one or more layout patterns of cut feature layout patterns 608 a, 608 b, 608 c, 908 a or 908 b. In comparison with layout design 800 of FIG. 8, cut feature layout patterns 908 a, 908 b of layout design 900 replace cut feature layout patterns 808 e, 808 f, and similar detailed description is therefore omitted.

Cut feature layout patterns 908 a and 908 b are next to each other in the first direction X. Cut feature layout patterns 908 a and 908 b overlap power rail layout pattern 306 b and gate layout pattern 304 a. Other configurations or quantities of cut feature layout patterns in the set of cut feature layout patterns 808 are within the scope of the present disclosure.

In comparison with layout design 800 of FIG. 8, set of metal over diffusion layout patterns 914 of layout design 900 replace set of metal over diffusion layout patterns 814, and similar detailed description is therefore omitted. Set of metal over diffusion layout patterns 914 includes one or more layout patterns of metal over diffusion layout patterns 812, 914 a or 914 b. In comparison with layout design 800 of FIG. 8, metal over diffusion layout patterns 914 a and 914 b of layout design 900 replace metal over diffusion layout pattern 810, and similar detailed description is therefore omitted.

Metal over diffusion layout patterns 914 a, 914 b are similar to corresponding metal over diffusion layout patterns 614 a, 614 b of FIG. 6, and similar detailed description is therefore omitted. Metal over diffusion layout patterns 914 a and 914 b are separated from each other in the second direction Y. Metal over diffusion layout patterns 914 a and 914 b overlap corresponding active region layout patterns 802 and 804. One or more metal over diffusion layout patterns of the set of metal over diffusion layout patterns 310, 310′, 510, 614, 714, 814 or 914 is useable to manufacture a corresponding contact (not labelled) similar to contact 410 a, 410 b of FIG. 4A or contact 412 of FIG. 4B. Other configurations or quantities of layout patterns in the set of metal over diffusion layout patterns 914 are within the scope of the present disclosure.

In comparison with layout design 800 of FIG. 8, set of via layout patterns 942 of layout design 900 replaces set of via layout patterns 842, and similar detailed description is therefore omitted. Set of via layout patterns 942 includes one or more layout patterns of via layout patterns 942 a or 942 d. In comparison with layout design 800 of FIG. 8, via layout pattern 942 a of layout design 900 replaces via layout pattern 842 c, and similar detailed description is therefore omitted. Via layout pattern 942 d is similar to via layout pattern 642 a, 642 d or 842 c of layout design 800 of FIG. 8, and similar detailed description is therefore omitted.

Via layout pattern 942 a is positioned between conductive feature layout pattern 816 d and gate layout pattern 304 a. Via layout pattern 942 a is positioned where conductive feature layout pattern 816 d overlaps gate layout pattern 304 a.

Via layout pattern 942 d is positioned between conductive feature layout pattern 816 a and gate layout pattern 304 a. Via layout pattern 942 d is positioned where conductive feature layout pattern 816 a overlaps gate layout pattern 304 a. Other configurations or quantities of one or via layout patterns of the set of via layout patterns 942 are within the scope of the present disclosure.

Via layout pattern 942 a and via layout pattern 942 d are separated from each other in the second direction Y by a distance DVG_VD1. In some embodiments, distance DVG_VD1 is measured from the center of via layout pattern 942 a and via layout pattern 942 d.

Via layout pattern 642 a and via layout pattern 942 d are separated from each other in the second direction Y by a distance DVG_VD2. In some embodiments, distance DVG_VD2 is measured from the center of via layout pattern 642 a and via layout pattern 942 d.

Each of the via layout patterns of the set of via layout patterns 942 is separated from the set of cut feature layout patterns 808 or 908 in the second direction Y by a distance S1D. For example, via layout pattern 942 a is separated in the second direction Y from cut feature layout pattern 808 b by distance S1D. Similarly, via layout pattern 942 d is separated in the second direction Y from cut feature layout pattern 808 a by distance S1D. In some embodiments, distance S1D is measured from the edge of via layout pattern 942 a or 942 d and the edge of cut feature layout pattern 808 a.

Each of the via layout patterns of the set of via layout patterns 642 in layout design 900 is separated from the set of cut feature layout patterns 608′ or 908 in the second direction Y by a distance S1D. For example, via layout pattern 642 a is separated in the second direction Y from cut feature layout pattern 608 b or 908 a by distance S1D. Similarly, via layout pattern 642 d is separated in the second direction Y from cut feature layout pattern 608 b or 608 c by distance S1D. In some embodiments, distance S1D is measured from the edge of via layout pattern 642 a or 642 d and the edge of cut feature layout pattern 608 b, 608 c or 908 a.

The set of active region layout patterns 830 are separated from the set of cut feature layout patterns 808 or 908 in the second direction Y by distance S2D. For example, active region layout pattern 804 is separated from cut feature layout pattern 808 a, 808 d or 808 b in the second direction Y by distance S2D. Similarly, active region layout pattern 802 is separated from cut feature layout pattern 808 a, 808 b, 908 a or 908 b in the second direction Y by distance S2D. In some embodiments, distance S2D is measured from an edge of active region layout pattern 804 and the edge of cut feature layout pattern 808 a, 808 d or 808 b. In some embodiments, distance S2D is measured from an edge of active region layout pattern 802 and the edge of cut feature layout pattern 808 a, 808 b, 908 a or 908 b.

The set of active region layout patterns 630 are separated from the set of cut feature layout patterns 608′ or 908 in the second direction Y by distance S2D. For example, active region layout pattern 604 is separated from cut feature layout pattern 608 a, 608 b, 908 a or 908 b in the second direction Y by distance S2D. Similarly, active region layout pattern 602 is separated from cut feature layout pattern 608 a, 608 b or 608 c in the second direction Y by distance S2D. In some embodiments, distance S2D is measured from an edge of active region layout pattern 604 and the edge of cut feature layout pattern 608 a, 608 b, 908 a or 908 b. In some embodiments, distance S2D is measured from an edge of active region layout pattern 602 and the edge of cut feature layout pattern 608 a, 608 b or 608 c.

Active region layout pattern 602, 802 of layout design 900 is separated in the second direction Y from the corresponding active region layout pattern 604, 804 by distance S3D. In some embodiments, distance S3D is measured from the edge of active region layout pattern 602, 802 and the edge of corresponding active region layout pattern 604, 804.

Fin layout pattern 602 a, 604 a, 802 a, 804 a of layout design 900 is separated from corresponding fin layout pattern 602 b, 604 b, 802 b, 804 b in the second direction Y by the fin pitch P2D. In some embodiments, fin pitch P2D is measured from the center of fin layout pattern 602 a, 604 a, 802 a, 804 a to the center of corresponding fin layout patterns 602 b, 604 b, 802 b, 804 b. Other configurations or quantities of layout patterns in the set of fin layout patterns 603, 605, 803 or 805 are within the scope of the present disclosure.

In some embodiments, a relationship between distance S3D and fin pitch P2D is expressed by formula 17: S3D≤2.5*P2D  (17)

In some embodiments, formula 17 corresponds to a relationship between the distance (e.g., S3D) between the active region layout patterns and the fin pitch (e.g., P2D) of the active region layout patterns.

In some embodiments, a relationship between distance S1D and distance S3D is expressed by formula 18: S1D≥0.3*S3D  (18)

In some embodiments, formula 18 corresponds to a relationship between the VG distance (e.g., S1D) between the set of via layout patterns 642 or 942 and the set of cut feature layout patterns 608′, 808 or 908, and the distance (e.g., S3D) between the active region layout patterns 802 and 804 or active region layout patterns 602 and 604.

In some embodiments, a relationship between distance S2D and distance S3D is expressed by formula 19: S2D≥0.2*S3D  (19)

In some embodiments, formula 19 corresponds to a relationship between the set of cut feature layout patterns 608′, 808 or 908 and the set of active region layout patterns 630 or 830. In some embodiments, layout designs (e.g., layout design 900) that satisfy formula 18 results in the set of cut feature layout patterns 608′, 808 or 908 being sufficiently separated from the set of active region layout patterns 630 or 830 in order to overcome process limitations attributed to operation 106 of method 100.

In some embodiments, a relationship between distance S3D and distance DVG_VD1 is expressed by formula 20: 1.5*S3D≥DVG_VD1≥0.8*S3D  (20)

In some embodiments, formula 20 corresponds to a minimum and maximum distance relationship between VG via layout patterns (e.g., set of via layout patterns 942) in the second direction Y.

In some embodiments, a relationship between distance S3D and distance DVG_VD2 is expressed by formula 21: 3.6*S3D≥DVG_VD2≥2.3*S3D  (21)

In some embodiments, formula 21 corresponds to a minimum and maximum distance relationship between VG via layout patterns (e.g., set of via layout patterns 642 and 942) in the second direction Y.

In some embodiments, layout designs (e.g., layout design 900) that satisfy formulas 18 and 20 results in the set of via layout patterns 942 being sufficiently separated from the set of cut feature layout patterns 808 or 908 in order to overcome process limitations attributed to operation 106 of method 100.

In some embodiments, formulas 17-21 correspond to one or more design rules of layout design 900 and methods 100-200 of FIGS. 1-2.

In some embodiments, layout designs that satisfy the one or more design rules specified by formulas 17-21 results in layout designs (e.g., layout design 900) which account for process limitations, and are capable of being used to consistently manufacture corresponding integrated circuits by semiconductor fabrication processes, such as methods 100-200 of FIGS. 1-2.

FIGS. 10A-10B is a flowchart of a method 1000 of generating a layout design of an integrated circuit in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method 1000 depicted in FIGS. 10A-10B, and that some other processes may only be briefly described herein. In some embodiments, the method 1000 is usable to generate one or more layout designs, such as layout design 300A (FIG. 3A), layout design 300B (FIG. 3B), layout design 500A (FIG. 5A), layout design 500B (FIG. 5B), layout design 600 (FIG. 6), layout design 700 (FIG. 7), layout design 800 (FIG. 8) or layout design 900 (FIG. 9) of an integrated circuit, such as integrated circuit 400A (FIG. 4A) or integrated circuit 400B (FIG. 4B). In some embodiments, method 1000 is performed by a processing device (e.g., processor 1102 (FIG. 11)) configured to execute instructions for generating layout design 300A (FIG. 3A), layout design 300B (FIG. 3B), layout design 500A (FIG. 5A), layout design 500B (FIG. 5B), layout design 600 (FIG. 6), layout design 700 (FIG. 7), layout design 800 (FIG. 8) or layout design 900 (FIG. 9). Method 1000 is an embodiment of operation 102 of method 100 (FIG. 1). In some embodiments, method 1000 is an implementation of method 200 (FIG. 2).

In operation 1002 of method 1000, a set of active region layout patterns is generated. In some embodiments, the set of active region layout patterns of method 1000 includes one or more patterns of the set of active region layout patterns 602, 604, 802, 804 of FIGS. 6-9, and detailed description of these layout patterns is therefore omitted.

In operation 1004 of method 1000, the set of active region layout patterns is placed on a first layout level of a layout design (e.g., layout design 300A-300B, 500A-500B or 600-900). In some embodiments, the first layout level of method 1000 corresponds to the OD layout level.

In operation 1006 of method 1000, a set of fin layout patterns is generated. In some embodiments, the set of fin layout patterns of method 1000 includes one or more patterns of the set of fin layout patterns 602 a, 602 b, 604 a, 604 b, 802 a, 802 b, 804 a, 804 b of FIGS. 6-9, and detailed description of these layout patterns is therefore omitted.

In operation 1008 of method 1000, the set of fin layout patterns is placed on a second layout level of the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900). In some embodiments, the second layout level of method 1000 corresponds to the FIN layout level. In some embodiments, the second layout level of method 1000 is the same as the first layout level. In some embodiments, the second layout level of method 1000 is different from the first layout level. In some embodiments, the second layout level of method 1000 is above the first layout level. In some embodiments, the second layout level of method 1000 is below the first layout level.

In operation 1010 of method 1000, a set of gate layout patterns is generated. In some embodiments, the set of gate layout patterns of method 1000 includes one or more gate layout patterns 304 a, 404 b, 504 a, 704 a or 704 b of layout designs 300A-300B, 500A-500B or 600-900 of FIGS. 3A-3B, 5A-5B & 6-9, and detailed description of these layout patterns is therefore omitted.

In operation 1012 of method 1000, the set of gate layout patterns is placed on a third layout level of layout design (e.g., layout design 300A-300B, 500A-500B or 600-900). In some embodiments, the third layout level of method 1000 corresponds to the Poly layout level or MD layout level. In some embodiments, the third layout level of method 1000 is different from the first layout level and the second layout level. In some embodiments, the third layout level of method 1000 is above one or more of the first or second layout level of method 1000. In some embodiments, the third layout level of method 1000 is below one or more of the first or second layout level.

In operation 1014 of method 1000, a first set of conductive feature layout patterns is generated. In some embodiments, the first set of conductive feature layout patterns of method 1000 includes one or more patterns of conductive feature layout patterns 306 a, 306 b, 314 a, 314 b, 314 c, 314 d, 314 e, 314 f, 316 a, 316 b, 316 c, 316 d, 316 e, 316 f, 316 g, 516 a, 516 d, 516 e, 516 f, 516 g or 806 b of FIGS. 3A-3B, 5A-5B & 6-9, or one or more patterns of the set of conductive feature layout patterns 306, 314, 316, 516, 616, 716, 806, 816 or 916 of FIGS. 3A-3B, 5A-5B & 6-9 or one or more conductive feature layout patterns shown in layout designs 300A-300B, 500A-500B & 600-900, and detailed description of these layout patterns is therefore omitted. In some embodiments, the first set of conductive feature layout patterns of method 1000 includes a set of power rail layout patterns (e.g., set of power rail layout patterns 306 or 806), and detailed description of these layout patterns is therefore omitted.

In operation 1016 of method 1000, the first set of conductive feature layout patterns is placed on a fourth layout level of the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900). In some embodiments, the fourth layout level of method 1000 corresponds to the M0 layout level. In some embodiments, the fourth layout level of method 1000 corresponds to the M1 or M2 layout level. In some embodiments, the fourth layout level of method 1000 is different from the first layout level, the second layout level or the third layout level of method 1000. In some embodiments, the fourth layout level of method 1000 is above one or more of the first layout level, the second layout level or the third layout level of method 1000. In some embodiments, the fourth layout level of method 1000 is below one or more of the first layout level, the second layout level or the third layout level of method 1000. In some embodiments, one or more conductive feature layout patterns of the first set of conductive feature layout patterns of method 1000 is placed on one or more of gridlines 302 a, 302 b, 302 c, 302 d, 302 a′, 302 b′, 302 c′ or 302 d′ of layout design 300A-300B, 500A-500B or 600-900.

In operation 1018 of method 1000, a first set of via layout patterns is generated. In some embodiments, the first set of via layout patterns of method 1000 includes one or more patterns of via layout patterns 330, 332, 540 a, 540 b, 542, 544, 642 a, 642 b, 642 c, 642 d, 722, 742 b, 842 a, 842 c, 842 d, 942 a or 942 d of FIGS. 3A-3B, 5A-5B & 6-9 or one or more via layout patterns shown in layout designs 300A-300B, 500A-500B & 600-900, or one or more via layout patterns in the set of via layout patterns 340, and detailed description of these layout patterns is therefore omitted.

In operation 1020 of method 1000, the first set of via layout patterns is placed between the third layout level and the fourth layout level of the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900). In some embodiments, the first set of via layout patterns of method 1000 is placed on the VG layout level of the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900). In some embodiments, the first set of via layout patterns of method 1000 is placed between the one or more gate layout patterns and the one or more conductive feature layout patterns of the first set of conductive feature layout patterns.

In operation 1022 of method 1000, a set of metal over diffusion layout patterns is generated. In some embodiments, the set of metal over diffusion layout patterns of method 1000 includes one or more layout patterns of metal over diffusion layout patterns 310 a, 310 b, 312, 512, 610, 612, 614 a, 614 b, 710, 712, 810, 812, 814 a, 814 b, 914 a or 914 b of FIGS. 3A-3B, 5A-5B & 6-9, or one or more metal over diffusion layout patterns shown in layout designs 300A-300B, 500A-500B & 600-900, and detailed description of these layout patterns is therefore omitted.

In operation 1024 of method 1000, the set of metal over diffusion layout patterns is placed on the third layout level of the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900). In some embodiments, the third layout level of method 1000 corresponds to the MD layout level.

In operation 1026 of method 1000, a second set of via layout patterns is generated. In some embodiments, the second set of via layout patterns of method 1000 includes one or more patterns of via layout patterns 320 a, 322 a, 322 b, 324, 522 b, 622, 624, 724, 822 or 824 of FIGS. 3A-3B, 5A-5B & 6-9, or one or more via layout patterns shown in layout designs 300A-300B, 500A-500B & 600-900, or one or more via layout patterns in the set of via layout patterns 320, 320′, and detailed description of these layout patterns is therefore omitted.

In operation 1028 of method 1000, the second set of via layout patterns is placed between the third layout level and the fourth layout level of the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900). In some embodiments, the second set of via layout patterns of method 1000 is placed on the via over diffusion (VD) layout level of the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900). In some embodiments, the second set of via layout patterns of method 1000 is placed between one or more metal over diffusion layout patterns of the set of metal over diffusion layout patterns and one or more conductive feature layout patterns of the first set of conductive feature layout patterns.

In operation 1030 of method 1000, a set of cut feature layout patterns is generated. In some embodiments, the set of cut feature layout patterns of method 1000 includes one or more cut feature layout patterns 308 a, 308 b, 608 a, 608 b, 608 c, 608 d, 708 a, 708 b, 808 a, 808 b, 808 e, 808 f, 908 a or 908 b of the set of cut feature layout patterns 308, 608, 708, 808 or 908, (FIG. 9) or one or more cut feature layout patterns shown in layout designs 300A-300B, 500A-500B & 600-900, and detailed description of these layout patterns is therefore omitted.

In operation 1024 of method 1000, the set of cut feature layout patterns is placed on one or more of the first, second, third or fourth layout level of the layout design (e.g., layout design 300A-300B, 500A-500B or 600-900).

In some embodiments, one or more of the operations of method 1000 is not performed.

One or more of the operations of methods 100, 200 or 1000 is performed by a processing device 1102 configured to execute instructions 1106 for manufacturing an integrated circuit, such as integrated circuit 400A-400B. In some embodiments, one or more operations of methods 100, 200 or 1000 is performed using a same processing device as that used in a different one or more operations of methods 100, 200 or 1000. In some embodiments, a different processing device is used to perform one or more operations of methods 100, 200 or 1000 from that used to perform a different one or more operations of methods 100, 200 or 1000.

FIG. 11 is a schematic view of a system 1100 for designing an IC layout design in accordance with some embodiments. In some embodiments, system 1100 generates or places one or more IC layout designs described herein. System 1100 includes a hardware processor 1102 and a non-transitory, computer readable storage medium 1104 encoded, i.e., storing, with the computer program code 1106, i.e., a set of executable instructions. Computer readable storage medium 1104 is configured for interfacing with manufacturing machines for producing the integrated circuit. The processor 1102 is electrically coupled to the computer readable storage medium 1104 via a bus 1108. The processor 1102 is also electrically coupled to an I/O interface 1110 by bus 1108. A network interface 1112 is also electrically connected to the processor 1102 via bus 1108. Network interface 1112 is connected to a network 1114, so that processor 1102 and computer readable storage medium 1104 are capable of connecting to external elements via network 1114. The processor 1102 is configured to execute the computer program code 1106 encoded in the computer readable storage medium 1104 in order to cause system 1100 to be usable for performing a portion or all of the operations as described in method 100, 200 or 1000.

In some embodiments, the processor 1102 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In some embodiments, the computer readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, the computer readable storage medium 1104 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In some embodiments using optical disks, the computer readable storage medium 1104 includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).

In some embodiments, the storage medium 1104 stores the computer program code 1106 configured to cause system 1100 to perform method 100, 200 or 1000. In some embodiments, the storage medium 1104 also stores information needed for performing method 100, 200 or 1000 as well as information generated during performing method 100, 200 or 1000, such as layout design 1116, user interface 1118 and design rules 1120, and/or a set of executable instructions to perform the operation of method 100, 200 or 1000. In some embodiments, layout design 1116 comprises one or more of layout designs 300A-300B, 500A-500B or 600-900. In some embodiments, layout design 1116 comprises one or more layout patterns of layout designs 300A-300B, 500A-500B or 600-900.

In some embodiments, the storage medium 1104 stores instructions (e.g., computer program code 1106) for interfacing with manufacturing machines. The instructions (e.g., computer program code 1106) enable processor 1102 to generate manufacturing instructions readable by the manufacturing machines to effectively implement method 100, 200 or 1000 during a manufacturing process.

System 1100 includes I/O interface 1110. I/O interface 1110 is coupled to external circuitry. In some embodiments, I/O interface 1110 includes a keyboard, keypad, mouse, trackball, trackpad, and/or cursor direction keys for communicating information and commands to processor 1102.

System 1100 also includes network interface 1112 coupled to the processor 1102. Network interface 1112 allows system 1100 to communicate with network 1114, to which one or more other computer systems are connected. Network interface 1112 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interface such as ETHERNET, USB, or IEEE-1394. In some embodiments, method 100, 200 or 1000 is implemented in two or more systems 1100, and information such as layout design, user interface and design rules, are exchanged between different systems 1100 by network 1114.

System 1100 is configured to receive information related to a layout design through I/O interface 1110 or network interface 1112. The information is transferred to processor 1102 by bus 1108 to determine a layout design for producing an integrated circuit, e.g., integrated circuit 400A-400B. The layout design is then stored in computer readable medium 1104 as layout design 1116. System 1100 is configured to receive information related to a user interface through I/O interface 1110 or network interface 1112. The information is stored in computer readable medium 1104 as user interface 1118. System 1100 is configured to receive information related to one or more design rules through I/O interface 1110 or network interface 1112. The information is stored in computer readable medium 1104 as design rules 1120. In some embodiments, the set of design rules 1120 includes one or more design rules of layout design 300A-300B, layout design 500A-500B or layout design 600-900. In some embodiments, the set of design rules 1120 includes one or more design rules of formulas 1-21, VG landing design rules of layout design 500A-500B, M0 metal track design rules of layout design 500-A-500B or MD design rules of layout design 300A-300B.

In some embodiments, method 100, 200 or 1000 is implemented as a standalone software application for execution by a processor. In some embodiments, method 100, 200 or 1000 is implemented as a software application that is a part of an additional software application. In some embodiments, method 100, 200 or 1000 is implemented as a plug-in to a software application. In some embodiments, method 100, 200 or 1000 is implemented as a software application that is a portion of an EDA tool. In some embodiments, method 100, 200 or 1000 is implemented as a software application that is used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of the integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer readable medium. In some embodiments, the layout is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the layout is generated based on a netlist which is created based on the schematic design. In some embodiments, method 100, 200 or 1000 is implemented by a manufacturing device to manufacture an integrated circuit (e.g., integrated circuit 400A-400B) using a set of masks manufactured based on one or more layout designs (e.g., layout design 300A-300B, 500A-500B, or 600-900) generated by system 1100. System 1100 of FIG. 11 generates layout designs (e.g., layout design 300A-300B, 500A-500B, or 600-900) of an integrated circuit (e.g, integrated circuit 400A-400B) that are smaller than other approaches. System 1100 of FIG. 11 generates layout designs (e.g., layout design 300A-300B, 500A-500B, or 600-900) of an integrated circuit (e.g, integrated circuit 400A-400B) that have improved gate density than other approaches. In some embodiments, by using one or more layout designs of the present application, the integrated circuit manufactured by the corresponding one or more layout designs has a gate density that is at least 10% greater compared to other approaches.

FIG. 12 is a block diagram of an integrated circuit (IC) manufacturing system 1200, and an IC manufacturing flow associated therewith, in accordance with at least one embodiment of the present disclosure.

In FIG. 12, IC manufacturing system 1200 includes entities, such as a design house 1220, a mask house 1230, and an IC manufacturer/fabricator (“fab”) 1240, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device 1260. The entities in system 1200 are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house 1220, mask house 1230, and IC fab 1240 is owned by a single larger company. In some embodiments, two or more of design house 1220, mask house 1230, and IC fab 1240 coexist in a common facility and use common resources.

Design house (or design team) 1220 generates an IC design layout 1222. IC design layout 1222 includes various geometrical patterns designed for an IC device 1260. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device 1260 to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout 1222 includes various IC features, such as an active region, gate electrode, source electrode and drain electrode, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house 1220 implements a proper design procedure to form IC design layout 1222. The design procedure includes one or more of logic design, physical design or place and route. IC design layout 1222 is presented in one or more data files having information of the geometrical patterns. For example, IC design layout 1222 can be expressed in a GDSII file format or DFII file format.

Mask house 1230 includes data preparation 1252 and mask fabrication 1244. Mask house 1230 uses IC design layout 1222 to manufacture one or more masks to be used for fabricating the various layers of IC device 1260 according to IC design layout 1222. Mask house 1230 performs mask data preparation 1252, where IC design layout 1222 is translated into a representative data file (“RDF”). Mask data preparation 1252 provides the RDF to mask fabrication 1244. Mask fabrication 1244 includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by mask data preparation 1252 to comply with particular characteristics of the mask writer and/or requirements of IC fab 1240. In FIG. 12, mask data preparation 1252 and mask fabrication 1244 are illustrated as separate elements. In some embodiments, mask data preparation 1252 and mask fabrication 1244 can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation 1252 includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout 1222. In some embodiments, mask data preparation 1252 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation 1252 includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during mask fabrication 1244, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation 1252 includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab 1240 to fabricate IC device 1260. LPC simulates this processing based on IC design layout 1222 to create a simulated manufactured device, such as IC device 1260. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout 1222.

It should be understood that the above description of mask data preparation 1252 has been simplified for the purposes of clarity. In some embodiments, data preparation 1252 includes additional features such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to IC design layout 1222 during data preparation 1252 may be executed in a variety of different orders.

After mask data preparation 1252 and during mask fabrication 1244, a mask or a group of masks are fabricated based on the modified IC design layout. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask can be formed in various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using a phase shift technology. In the phase shift mask (PSM), various features in the pattern formed on the mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication 1244 is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etching regions in the semiconductor wafer, and/or in other suitable processes.

IC fab 1240 is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab 1240 is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.

IC fab 1240 uses the mask (or masks) fabricated by mask house 1230 to fabricate IC device 1260. Thus, IC fab 1240 at least indirectly uses IC design layout 1222 to fabricate IC device 1260. In some embodiments, a semiconductor wafer 1252 is fabricated by IC fab 1240 using the mask (or masks) to form IC device 1260. Semiconductor wafer 1252 includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g., system 1200 of FIG. 12), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference.

One aspect of this description relates to a system for designing an integrated circuit. In some embodiments, the system includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium, where the processor is configured to execute the instructions for generating a layout design of the integrated circuit, the layout design having a set of design rules. In some embodiments, the generating of the layout design includes placing a set of gate layout patterns on a first layout level, the set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction, the set of gate layout patterns extending in a second direction different from the first direction; placing a cut feature layout pattern over the set of gate layout patterns, the cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns; placing a first conductive feature layout pattern on a second layout level different from the first layout level, the first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and the first conductive feature layout pattern extending in the first direction; and placing a first via layout patterns between the first conductive feature layout pattern and the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being located where the first conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns. In some embodiments, the processor configured to the execute instructions for the generating of the layout design further includes placing a first active region layout pattern on a third layout level different from the first layout level and the second layout level, and the first active region layout pattern extending in the first direction; placing a second active region layout pattern on the third layout level, extending in the first direction and being separated from the first active region layout pattern in the second direction by a first distance (s1), the set of design rules of the layout design including the first distance; placing a first contact layout pattern on the first layout level, extending in the second direction and overlapping the first active region layout pattern and the second active region layout pattern; and placing a second contact layout pattern on the first layout level, extending in the second direction, overlapping the first active region layout pattern and the second active region layout pattern, and being separated from the first contact layout pattern in the first direction. In some embodiments, the processor configured to execute the instructions for the generating of the layout design, the set of design rules of the layout design further including a second distance between the cut feature layout pattern and the first active region layout pattern or the second active region layout pattern in the second direction, and being expressed by s2≥0.2*s1. In some embodiments, the processor configured to execute the instructions for the generating of the layout design, the set of design rules of the layout design further including a third distance between the first via layout pattern and the cut feature layout pattern in the second direction, and being expressed by s3≥0.3*s1. In some embodiments, the processor configured to execute the instructions for the generating of the layout design further includes placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern extending in the first direction, being over the first active region layout pattern, overlapping a second gate layout pattern of the set of gate layout patterns, and being separated from the first conductive feature layout pattern in the first direction; and placing a second via layout pattern between the second conductive feature layout pattern and the second gate layout pattern of the set of gate layout patterns, and the second via layout pattern being located where the second conductive feature layout pattern overlaps the second gate layout pattern of the set of gate layout patterns; where the second gate layout pattern is separated from the first gate layout pattern by a first poly pitch in the first direction; and the second via layout pattern is separated from the first via layout pattern by a second distance in the first direction, and is expressed by 1.1*p1≥dvg1≥0.9*p1, where the set of design rules of the layout design further includes the first poly pitch and the second distance. In some embodiments, the processor configured to execute the instructions for the generating of the layout design further includes placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern extending in the first direction, being over the second active region layout pattern, overlapping the first gate layout pattern of the set of gate layout patterns, and being separated from the first conductive feature layout pattern in the second direction; and placing a second via layout pattern between the second conductive feature layout pattern and the first gate layout pattern of the set of gate layout patterns, and the second via layout pattern being located where the second conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns; where the second via layout pattern is separated from the first via layout pattern by a second distance in the second direction, and is expressed by 1.5*s1≥dvg2≥0.8*s1 where the set of design rules of the layout design further includes the second distance. In some embodiments, the processor configured to execute the instructions for the generating of the layout design further includes placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern extending in the first direction, and being separated from the first conductive feature layout pattern in the second direction; and placing a second via layout pattern between the second conductive feature layout pattern and the first contact layout pattern or the second contact layout pattern, the second via layout pattern being located where the second conductive feature layout pattern overlaps the first contact layout pattern or the second contact layout pattern.

Another aspect of this description relates to an integrated circuit. In some embodiments, the integrated circuit includes a set of gates including at least a first gate, a second gate and a third gate, the first gate and the second gate being separated from each other in a first direction by a first pitch, the first gate and the third gate being separated from each other in a second direction different from the first direction by a removed gate portion, the set of gates being located on a first level and extending in the second direction. In some embodiments, the integrated circuit further includes a first conductive structure extending in the first direction and being located on a second level different from the first level. In some embodiments, the integrated circuit further includes a second conductive structure extending in the first direction, being separated from the first conductive structure in the first direction and being located on the second level. In some embodiments, the integrated circuit further includes a third conductive structure extending in the first direction, being separated from the first conductive structure in the second direction and being located on the second level. In some embodiments, the integrated circuit further includes a first via between the first conductive structure and the first gate, the first via coupling the first conductive structure to the first gate, and the first via being located where the first conductive structure overlaps the first gate. In some embodiments, the integrated circuit further includes a second via between the second conductive structure and the second gate, the second via coupling the second conductive structure to the second gate, and the second via being located where the second conductive structure overlaps the second gate. In some embodiments, the integrated circuit further includes a third via between the third conductive structure and the third gate, the third via coupling the third conductive structure to the third gate, and the third via being located where the third conductive structure overlaps the third gate, where the first via, the second via and the third via are in a right angle configuration. In some embodiments, the integrated circuit further includes a first active region on a third level different from the first level and the second level, and the first active region extending in the first direction; and a second active region on the third level, extending in the first direction and being separated from the first active region in the second direction by a first distance (s1), where the first conductive structure and the second conductive structure are over the first active region, and the third conductive structure is over the second active region. In some embodiments, the integrated circuit further includes a set of fins on the first active region or the second active region, and extending in the first direction, each fin of the set of fins being separated from an adjacent fin of the set of fins in the second direction by a second pitch (p2), and p2 is related to s1 by s1≤2.5*p2. In some embodiments, at least the first active region or the second active region is separated from the removed gate portion by a second distance (s2) in the second direction, and is expressed by s2≥0.2*s1. In some embodiments, at least the first via, the second via or the third via is separated from the removed gate portion by a third distance (s3) in the second direction, and is expressed by s3≥0.3*s1. In some embodiments, the second via is separated from the first via by a fourth distance (dvg1) in the first direction, and is expressed by 1.1*p1≥dvg1≥0.9*p1, where p1 is the first pitch between the first gate and the second gate in the first direction. In some embodiments, the third via is separated from the first via by a fourth distance (dvg2) in the second direction, and is expressed by 1.5*s1≥dvg2≥0.8*s1.

Still another aspect of this description relates to a method of forming an integrated circuit. In some embodiments, the method includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules, and manufacturing the integrated circuit based on the layout design, the integrated circuit having the first gate of the set of gate structures. In some embodiments, the generating of the layout design includes generating a set of active region layout patterns extending in a first direction, being located on a first layout level, and each of the layout patterns of the set of active region layout patterns being separated from one another in a second direction different from the first direction; generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in the first direction by a first pitch, the set of gate layout patterns extending in the second direction and being located on a second layout level different from the first layout level; and generating a cut feature layout pattern corresponding to a cut region of at least a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction, being located on the first layout level and overlapping at least a first gate layout pattern of the set of gate layout patterns, the cut feature layout pattern being separated from the set of active region layout patterns in the second direction by at least a first distance, the first distance satisfying a first design rule of the set of design rules. In some embodiments, the generating the layout design of the integrated circuit further includes generating a first via layout pattern, the first via layout pattern being over the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being separated in the second direction from the cut feature layout pattern by a second distance, the second distance satisfying a second design rule of the set of design rules. In some embodiments, the generating the layout design of the integrated circuit further includes generating a set of conductive feature layout patterns based on a third design rule of the set of design rules, the set of conductive feature layout patterns extending in the first direction, overlapping at least the first gate layout pattern of the set of gate layout patterns, and being located on a third layout level different from the first layout level and the second layout level, each of the layout patterns of the set of conductive feature layout patterns being separated from an adjacent layout pattern of the set of conductive feature layout patterns in at least the second direction by a second pitch, and overlapping a corresponding gridline of a set of gridlines, where the first via layout pattern is between a first conductive feature layout pattern of the set of conductive feature layout patterns and the first gate layout pattern of the set of gate layout patterns, the first via layout pattern being located where the first conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns, and the third design rule of the set of design rules includes the second distance being greater than the second pitch. In some embodiments, the generating the layout design of the integrated circuit further includes generating a second via layout pattern, the second via layout pattern being over a second gate layout pattern of the set of gate layout patterns, and the second via layout pattern being separated in the second direction from the cut feature layout pattern by the second distance; and generating a third via layout pattern, the third via layout pattern being over the first gate layout pattern of the set of gate layout patterns, and the third via layout pattern being separated in the second direction from the cut feature layout pattern by a third distance, the third distance satisfying the second design rule of the set of design rules. In some embodiments, the first via layout pattern, the second via layout pattern and the third via layout pattern are positioned in a right-angle configuration. In some embodiments, the generating the set of conductive feature layout patterns includes generating the first conductive feature layout pattern of the set of conductive feature layout patterns based on the third design rule of the set of design rules, the first conductive feature layout pattern overlapping the first gate layout pattern of the set of gate layout patterns and the first via layout pattern; generating a second conductive feature layout pattern of the set of conductive feature layout patterns based on the third design rule of the set of design rules, the second conductive feature layout pattern overlapping the second gate layout pattern of the set of gate layout patterns and the second via layout pattern, the second conductive feature layout pattern and the first conductive feature layout pattern are separated from each other in the first direction, and overlap a first gridline of the set of gridlines; and generating a third conductive feature layout pattern of the set of conductive feature layout patterns based on the third design rule of the set of design rules, the third conductive feature layout pattern overlapping the first gate layout pattern of the set of gate layout patterns and the third via layout pattern, the third conductive feature layout pattern is separated from at least the first conductive feature layout pattern in the second direction, and overlaps a second gridline of the set of gridlines. In some embodiments, the generating the set of conductive feature layout patterns includes generating a first contact layout pattern extending in the second direction, and being located on the first layout level, and overlapping a first active region layout pattern of the set of active region layout patterns and a second active region layout pattern of the set of active region layout patterns; and generating a second via layout pattern between a second conductive feature layout pattern of the set of conductive feature layout patterns and the first contact layout pattern, the second via layout pattern being located where the second conductive feature layout pattern of the set of conductive feature layout patterns overlaps the first contact layout pattern.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A system for designing an integrated circuit, the system comprises: a non-transitory computer readable medium configured to store executable instructions; and a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for: generating a layout design of the integrated circuit, the layout design having a set of design rules, wherein the generating of the layout design comprises: placing a set of gate layout patterns on a first layout level, the set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction, the set of gate layout patterns extending in a second direction different from the first direction; placing a cut feature layout pattern over the set of gate layout patterns, the cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns; placing a first conductive feature layout pattern on a second layout level different from the first layout level, the first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and the first conductive feature layout pattern extending in the first direction; and placing a first via layout pattern between the first conductive feature layout pattern and the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being located where the first conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns.
 2. The system of claim 1, wherein the processor configured to execute the instructions for the generating of the layout design further comprises: placing a first active region layout pattern on a third layout level different from the first layout level and the second layout level, and the first active region layout pattern extending in the first direction; placing a second active region layout pattern on the third layout level, extending in the first direction and being separated from the first active region layout pattern in the second direction by a first distance (S1), the set of design rules of the layout design including the first distance; placing a first contact layout pattern on the first layout level, extending in the second direction and overlapping the first active region layout pattern and the second active region layout pattern; and placing a second contact layout pattern on the first layout level, extending in the second direction, overlapping the first active region layout pattern and the second active region layout pattern, and being separated from the first contact layout pattern in the first direction.
 3. The system of claim 2, wherein the processor configured to execute the instructions for the generating of the layout design, the set of design rules of the layout design further including: a second distance between the cut feature layout pattern and the first active region layout pattern or the second active region layout pattern in the second direction, and being expressed by: S2≥0.2*S1.
 4. The system of claim 3, wherein the processor configured to execute the instructions for the generating of the layout design, the set of design rules of the layout design further including: a third distance between the first via layout pattern and the cut feature layout pattern in the second direction, and being expressed by: S3≥0.3*S1.
 5. The system of claim 2, wherein the processor configured to execute the instructions for the generating of the layout design further comprises: placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern extending in the first direction, being over the first active region layout pattern, overlapping a second gate layout pattern of the set of gate layout patterns, and being separated from the first conductive feature layout pattern in the first direction; and placing a second via layout pattern between the second conductive feature layout pattern and the second gate layout pattern of the set of gate layout patterns, and the second via layout pattern being located where the second conductive feature layout pattern overlaps the second gate layout pattern of the set of gate layout patterns; wherein the second gate layout pattern is separated from the first gate layout pattern by a first poly pitch in the first direction; and the second via layout pattern is separated from the first via layout pattern by a second distance in the first direction, and is expressed by: 1.1*P1≥DVG1≥0.9*P1, wherein the set of design rules of the layout design further includes the first poly pitch and the second distance.
 6. The system of claim 2, wherein the processor configured to execute the instructions for the generating of the layout design further comprises: placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern extending in the first direction, being over the second active region layout pattern, overlapping the first gate layout pattern of the set of gate layout patterns, and being separated from the first conductive feature layout pattern in the second direction; and placing a second via layout pattern between the second conductive feature layout pattern and the first gate layout pattern of the set of gate layout patterns, and the second via layout pattern being located where the second conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns; wherein the second via layout pattern is separated from the first via layout pattern by a second distance in the second direction, and is expressed by: 1.5*S1≥DVG2≥0.8*S1 wherein the set of design rules of the layout design further includes the second distance.
 7. The system of claim 2, wherein the processor configured to execute the instructions for the generating of the layout design further comprises: placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern extending in the first direction, and being separated from the first conductive feature layout pattern in the second direction; and placing a second via layout pattern between the second conductive feature layout pattern and the first contact layout pattern or the second contact layout pattern, the second via layout pattern being located where the second conductive feature layout pattern overlaps the first contact layout pattern or the second contact layout pattern.
 8. A method of forming an integrated circuit, the method comprising: generating, by a processor, a layout design of the integrated circuit based on a set of design rules, wherein the generating of the layout design comprises: generating a set of active region layout patterns extending in a first direction, being located on a first layout level, and each of the layout patterns of the set of active region layout patterns being separated from one another in a second direction different from the first direction; generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in the first direction by a first pitch, the set of gate layout patterns extending in the second direction and being located on a second layout level different from the first layout level; and generating a cut feature layout pattern corresponding to a cut region of at least a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction, being located on the first layout level and overlapping at least a first gate layout pattern of the set of gate layout patterns, the cut feature layout pattern being separated from the set of active region layout patterns in the second direction by at least a first distance, the first distance satisfying a first design rule of the set of design rules; manufacturing the integrated circuit based on the layout design, the integrated circuit having the first gate of the set of gate structures.
 9. The method of claim 8, wherein generating the layout design of the integrated circuit further comprises: generating a first via layout pattern, the first via layout pattern being over the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being separated in the second direction from the cut feature layout pattern by a second distance, the second distance satisfying a second design rule of the set of design rules.
 10. The method of claim 9, wherein generating the layout design of the integrated circuit further comprises: generating a set of conductive feature layout patterns based on a third design rule of the set of design rules, the set of conductive feature layout patterns extending in the first direction, overlapping at least the first gate layout pattern of the set of gate layout patterns, and being located on a third layout level different from the first layout level and the second layout level, each of the layout patterns of the set of conductive feature layout patterns being separated from an adjacent layout pattern of the set of conductive feature layout patterns in at least the second direction by a second pitch, and overlapping a corresponding gridline of a set of gridlines, wherein the first via layout pattern is between a first conductive feature layout pattern of the set of conductive feature layout patterns and the first gate layout pattern of the set of gate layout patterns, the first via layout pattern being located where the first conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns, and the third design rule of the set of design rules includes the second distance being greater than the second pitch.
 11. The method of claim 10, wherein generating the layout design of the integrated circuit further comprises: generating a second via layout pattern, the second via layout pattern being over a second gate layout pattern of the set of gate layout patterns, and the second via layout pattern being separated in the second direction from the cut feature layout pattern by the second distance; and generating a third via layout pattern, the third via layout pattern being over the first gate layout pattern of the set of gate layout patterns, and the third via layout pattern being separated in the second direction from the cut feature layout pattern by a third distance, the third distance satisfying the second design rule of the set of design rules; wherein the first via layout pattern, the second via layout pattern and the third via layout pattern are positioned in a right-angle configuration.
 12. The method of claim 11, wherein generating the set of conductive feature layout patterns comprises: generating the first conductive feature layout pattern of the set of conductive feature layout patterns based on the third design rule of the set of design rules, the first conductive feature layout pattern overlapping the first gate layout pattern of the set of gate layout patterns and the first via layout pattern; generating a second conductive feature layout pattern of the set of conductive feature layout patterns based on the third design rule of the set of design rules, the second conductive feature layout pattern overlapping the second gate layout pattern of the set of gate layout patterns and the second via layout pattern, the second conductive feature layout pattern and the first conductive feature layout pattern are separated from each other in the first direction, and overlap a first gridline of the set of gridlines; and generating a third conductive feature layout pattern of the set of conductive feature layout patterns based on the third design rule of the set of design rules, the third conductive feature layout pattern overlapping the first gate layout pattern of the set of gate layout patterns and the third via layout pattern, the third conductive feature layout pattern is separated from at least the first conductive feature layout pattern in the second direction, and overlaps a second gridline of the set of gridlines.
 13. The method of claim 10, wherein generating the set of conductive feature layout patterns comprises: generating a first contact layout pattern extending in the second direction, and being located on the first layout level, and overlapping a first active region layout pattern of the set of active region layout patterns and a second active region layout pattern of the set of active region layout patterns; and generating a second via layout pattern between a second conductive feature layout pattern of the set of conductive feature layout patterns and the first contact layout pattern, the second via layout pattern being located where the second conductive feature layout pattern of the set of conductive feature layout patterns overlaps the first contact layout pattern.
 14. A method of forming an integrated circuit, the method comprising: generating, by a processor, a layout design of the integrated circuit based on a set of design rules, wherein the generating of the layout design comprises: placing a set of gate layout patterns on a first layout level, the set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction, the set of gate layout patterns extending in a second direction different from the first direction; placing a cut feature layout pattern over the set of gate layout patterns, the cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns; placing a first contact layout pattern on the first layout level, extending in the second direction, and being separated from the set of gate layout patterns in the first direction; placing a first conductive feature layout pattern on a second layout level different from the first layout level, the first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and the first conductive feature layout pattern extending in the first direction; and placing a first via layout pattern between the first conductive feature layout pattern and the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being located where the first conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns; placing a first active region layout pattern on a third layout level different from the first layout level and the second layout level, and the first active region layout pattern extending in the first direction, and being overlapped by the first contact layout pattern; manufacturing the integrated circuit based on the layout design, the integrated circuit having the first gate of the set of gate structures.
 15. The method of claim 14, wherein the generating of the layout design further comprises: placing a second active region layout pattern on the third layout level, extending in the first direction and being separated from the first active region layout pattern in the second direction by a first distance, S1, the set of design rules of the layout design including the first distance, wherein the second active region layout pattern is overlapped by the first contact layout pattern; and placing a second contact layout pattern on the first layout level, extending in the second direction, being separated from the first contact layout pattern in the first direction, being separated from the set of gate layout patterns in the first direction, and overlapping the first active region layout pattern and the second active region layout pattern.
 16. The method of claim 15, wherein the generating of the layout design further comprises: placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern extending in the first direction, being separated from the first conductive feature layout pattern in the second direction and overlapping the first contact layout pattern or the second contact layout pattern; and placing a second via layout pattern between the second conductive feature layout pattern and the first contact layout pattern or the second contact layout pattern, the second via layout pattern being located where the second conductive feature layout pattern overlaps the first contact layout pattern or the second contact layout pattern.
 17. The method of claim 15, wherein the set of design rules of the layout design further including: a second distance between the cut feature layout pattern and the first active region layout pattern or the second active region layout pattern in the second direction, and is expressed by: S2≥0.2*S1.
 18. The method of claim 17, wherein the set of design rules of the layout design further including: a third distance between the cut feature layout pattern and the first via layout pattern in the second direction, and is expressed by: S3≥0.3*S1.
 19. The method of claim 15, wherein the generating of the layout design further comprises: placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern extending in the first direction, being separated from the first conductive feature layout pattern in the second direction, being over the second active region layout pattern, and overlapping the first gate layout pattern of the set of gate layout patterns; and placing a second via layout pattern between the second conductive feature layout pattern and the first gate layout pattern of the set of gate layout patterns, and the second via layout pattern being located where the second conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns; wherein the first via layout pattern and the second via layout pattern are separated from each other by a second distance in the second direction, and is expressed by: 1.5*S1≥DVG2≥0.8*S1 wherein the set of design rules of the layout design further includes the second distance.
 20. The method of claim 15, wherein the generating of the layout design further comprises: placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern extending in the first direction, being separated from the first conductive feature layout pattern in the second direction, being over the first active region layout pattern, and overlapping a second gate layout pattern of the set of gate layout patterns; and placing a second via layout pattern between the second conductive feature layout pattern and the second gate layout pattern of the set of gate layout patterns, and the second via layout pattern being located where the second conductive feature layout pattern overlaps the second gate layout pattern of the set of gate layout patterns; wherein the first gate layout pattern and the second gate layout pattern are separated from each other by a first poly pitch in the first direction; and the first via layout pattern and the second via layout pattern are separated from each other by a second distance in the first direction, and is expressed by: 1.1*P1≥DVG1≥0.9*P1, wherein the set of design rules of the layout design further includes the first poly pitch and the second distance. 